+#ifdef CONFIG_TX6_NAND
+#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
+#else
+#ifdef CONFIG_MMC_BOOT_SIZE
+#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
+#else
+#define TX6_FLASH_SZ 2
+#endif
+#endif /* CONFIG_TX6_NAND */
+
+#define TX6_DDR_SZ (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
+
+static char tx6_mem_table[] = {
+ '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
+ '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
+ '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
+ '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
+ '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
+ '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
+ '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
+ '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
+ '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
+ '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
+ '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
+ '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
+};
+
+static inline char tx6_mem_suffix(void)
+{
+ size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
+
+ debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
+ TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
+
+ if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
+ return '?';
+
+ return tx6_mem_table[mem_idx];
+};
+
+static struct {
+ uchar addr;
+ uchar rev;
+} tx6_mod_revs[] = {
+ { 0x3c, 1, },
+ { 0x32, 2, },
+ { 0x33, 3, },
+};
+
+static int tx6_get_mod_rev(unsigned int pmic_id)
+{
+ if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
+ return tx6_mod_revs[pmic_id].rev;
+
+ return 0;
+}
+
+static int tx6_pmic_probe(void)
+{
+ int i;
+
+ i2c_init_all();
+
+ for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
+ u8 i2c_addr = tx6_mod_revs[i].addr;
+ int ret = i2c_probe(i2c_addr);
+
+ if (ret == 0) {
+ debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
+ return i;
+ }
+ debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
+ }
+ return -EINVAL;
+}
+