karo: tx6: add support for TXUL-5014

[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c

diff --git a/board/karo/tx6/tx6ul.c b/board/karo/tx6/tx6ul.c
index bdb198001860684501fc33ce6a446d9321a8c7a8..702a1f838abdfa7de62517cfbaeaa530e418b3df 100644 (file)
--- a/board/karo/tx6/tx6ul.c
+++ b/board/karo/tx6/tx6ul.c
@@ -418,10 +418,15 @@ static bool tx6ul_temp_check_enabled = true;
 #define tx6ul_temp_check_enabled       0
 #endif
 
+#ifndef CONFIG_SYS_NAND_BLOCKS
+#define CONFIG_SYS_NAND_BLOCKS 0
+#endif
+
 static inline u8 tx6ul_mem_suffix(void)
 {
        return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
-               IS_ENABLED(CONFIG_TX6_EMMC);
+               IS_ENABLED(CONFIG_TX6_EMMC) +
+               CONFIG_SYS_NAND_BLOCKS / 2048 * 4;
 }
 
 #ifdef CONFIG_RN5T567
@@ -429,31 +434,49 @@ static inline u8 tx6ul_mem_suffix(void)
 #define VDD_RTC_VAL            rn5t_mV_to_regval_rtc(3000)
 #define VDD_CORE_VAL           rn5t_mV_to_regval(1300)         /* DCDC1 */
 #define VDD_CORE_VAL_LP                rn5t_mV_to_regval(900)
-#define VDD_DDR_VAL            rn5t_mV_to_regval(1350)         /* DCDC3 */
+#define VDD_DDR_VAL            rn5t_mV_to_regval(1350)         /* DCDC3 SDRAM 1.35V */
 #define VDD_DDR_VAL_LP         rn5t_mV_to_regval(1350)
-#define VDD_IO_EXT_VAL         rn5t_mV_to_regval(3300)         /* DCDC4 */
+#define VDD_IO_EXT_VAL         rn5t_mV_to_regval(3300)         /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */
 #define VDD_IO_EXT_VAL_LP      rn5t_mV_to_regval(3300)
-#define VDD_IO_INT_VAL         rn5t_mV_to_regval2(3300)        /* LDO1 */
+#define VDD_IO_INT_VAL         rn5t_mV_to_regval2(3300)        /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */
 #define VDD_IO_INT_VAL_LP      rn5t_mV_to_regval2(3300)
-#define VDD_ADC_VAL            rn5t_mV_to_regval2(3300)        /* LDO2 */
+#define VDD_ADC_VAL            rn5t_mV_to_regval2(3300)        /* LDO2 ADC */
 #define VDD_ADC_VAL_LP         rn5t_mV_to_regval2(3300)
-#define VDD_PMIC_VAL           rn5t_mV_to_regval2(2500)        /* LDO3 */
+#define VDD_PMIC_VAL           rn5t_mV_to_regval2(2500)        /* LDO3 PMIC */
 #define VDD_PMIC_VAL_LP                rn5t_mV_to_regval2(2500)
-#define VDD_CSI_VAL            rn5t_mV_to_regval2(3300)        /* LDO4 */
+#define VDD_CSI_VAL            rn5t_mV_to_regval2(3300)        /* LDO4 CSI */
 #define VDD_CSI_VAL_LP         rn5t_mV_to_regval2(3300)
+#define VDD_LDO5_VAL           rn5t_mV_to_regval2(1200)        /* LDO5 1.2V */
+#define LDOEN1_LDO1EN          (1 << 0)
+#define LDOEN1_LDO2EN          (1 << 1)
+#define LDOEN1_LDO3EN          (1 << 2)
+#define LDOEN1_LDO4EN          (1 << 3)
+#define LDOEN1_LDO5EN          (1 << 4)
+#define LDOEN1_VAL             (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN)
+#define LDOEN1_MASK            0x1f
+#define LDOEN2_LDORTC1EN       (1 << 4)
+#define LDOEN2_LDORTC2EN       (1 << 5)
+#define LDOEN2_VAL             LDOEN2_LDORTC1EN
+#define LDOEN2_MASK            0x30
 
 static struct pmic_regs rn5t567_regs[] = {
        { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
+       { RN5T567_SLPCNT, 0, },
+       { RN5T567_REPCNT, (3 << 4) | (0 << 1), },
        { RN5T567_DC1DAC, VDD_CORE_VAL, },
        { RN5T567_DC3DAC, VDD_DDR_VAL, },
        { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
        { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
        { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
        { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
-       { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
-       { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
-       { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
-       { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
+       { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC2CTL, DCnCTL_DIS, },
+       { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
+       { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+       { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+       { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
+       { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
        { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
        { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
        { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
@@ -464,12 +487,17 @@ static struct pmic_regs rn5t567_regs[] = {
        { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
        { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
        { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
-       { RN5T567_LDOEN1, 0x0f, ~0x1f, },
-       { RN5T567_LDOEN2, 0x10, ~0x30, },
-       { RN5T567_LDODIS, 0x10, ~0x1f, },
+       { RN5T567_LDO5DAC, VDD_LDO5_VAL, },
+       { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
+       { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
+       { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
+       { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
+       { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, },
+       { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, },
+       { RN5T567_LDODIS, 0x1f, ~0x1f, },
        { RN5T567_INTPOL, 0, },
        { RN5T567_INTEN, 0x3, },
-       { RN5T567_IREN, 0xf, },
+       { RN5T567_DCIREN, 0xf, },
        { RN5T567_EN_GPIR, 0, },
 };