#include <asm/processor.h>
#include <pci.h>
#include <libfdt.h>
+#include <post.h>
#include "../common/common.h"
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
-#if defined(CONFIG_KMETER1)
+#if defined(CONFIG_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elif !defined(CONFIG_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
static int board_init_i2c_busses(void)
{
I2C_MUX_DEVICE *dev = NULL;
- uchar *buf;
+ uchar *dtt_bus = (uchar *)"pca9547:70:a";
/* Set up the Bus for the DTTs */
- buf = (unsigned char *) getenv("dtt_bus");
- if (buf != NULL)
- dev = i2c_mux_ident_muxstring(buf);
- if (dev == NULL) {
+ dev = i2c_mux_ident_muxstring(dtt_bus);
+ if (dev == NULL)
printf("Error couldn't add Bus for DTT\n");
- printf("please setup dtt_bus to where your\n");
- printf("DTT is found.\n");
- }
+
return 0;
}
};
#endif
+static int piggy_present(void)
+{
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
+#if defined(CONFIG_KMVECT1)
+int ethernet_present(void)
+{
+ /* ethernet port connected to simple switch without piggy */
+ return 1;
+}
+#else
+int ethernet_present(void)
+{
+ return piggy_present();
+}
+#endif
+
+
int board_early_init_r(void)
{
struct km_bec_fpga *base =
setbits_8(&base->pgy_eth, 0x01);
/* enable the Unit LED (green) */
setbits_8(&base->oprth, WRL_BOOT);
+ /* enable Application Buffer */
+ setbits_8(&base->oprtl, OPRTL_XBUFENA);
#if defined(CONFIG_SUVD3)
/* configure UPMA for APP1 */
return 0;
}
+#if defined(CONFIG_KMVECT1)
+#include <mv88e6352.h>
+/* Marvell MV88E6122 switch configuration */
+static struct mv88e_sw_reg extsw_conf[] = {
+ /* port 1, FRONT_MDI, autoneg */
+ { PORT(1), PORT_PHY, NO_SPEED_FOR },
+ { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(1), PHY_1000_CTRL, NO_ADV },
+ { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, BP_MII (CPU), PHY mode, 100BASE */
+ { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
+ { PORT(5), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(5), PORT_PHY, SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /*
+ * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
+ * acc . MV-S300889-00D.pdf , clause 4.5
+ */
+ { PORT(5), 0x1A, 0xADB1 },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#endif
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMVECT1)
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ u8 tmp_reg;
+
+ /* Release mv88e6122 from reset */
+ tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
+ out_8(&base->res1[0], tmp_reg); /* GP28 as output */
+ tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
+ out_8(&base->gprt3, tmp_reg);
+
+ /* configure MV88E6122 switch */
+ char *name = "UEC2";
+
+ if (miiphy_set_current_dev(name))
+ return 0;
+
+ mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+ ARRAY_SIZE(extsw_conf));
+
+ mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+
+ if (piggy_present()) {
+ setenv("ethact", "UEC2");
+ setenv("netdev", "eth1");
+ puts("using PIGGY for network boot\n");
+ } else {
+ setenv("netdev", "eth0");
+ puts("using frontport for network boot\n");
+ }
+#endif
+
+#if defined(CONFIG_KMCOGE5NE)
+ struct bfticu_iomap *base =
+ (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+ u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
return 0;
}
u32 ddr_size_log2;
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
- out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
{
puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
- if (ethernet_present())
+ if (piggy_present())
puts(" with PIGGY.");
puts("\n");
return 0;
return 0;
}
#endif
+
+#if defined(CONFIG_POST)
+int post_hotkeys_pressed(void)
+{
+ int testpin = 0;
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
+ testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
+ debug("post_hotkeys_pressed: %d\n", !testpin);
+ return testpin;
+}
+
+ulong post_word_load(void)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
+ return in_le32(addr);
+
+}
+void post_word_store(ulong value)
+{
+ void* addr = (ulong *) (CPM_POST_WORD_ADDR);
+ debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
+ out_le32(addr, value);
+}
+
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ *vstart = CONFIG_SYS_MEMTEST_START;
+ *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
+ debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
+
+ return 0;
+}
+#endif
projects / karo-tx-uboot.git / blobdiff