board/mpl/common/flash.c: Fix GCC 4.6 build warning

[karo-tx-uboot.git] / board / mpl / common / flash.c

diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index 302d7a3d50ce4e9f666b8c475190b8c00887caa0..d5b63c01964ca7de5f449f2e76aa41774ed9f2c9 100644 (file)
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -38,7 +38,7 @@
 #include <common.h>
 
 #if !defined(CONFIG_PATI)
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <asm/processor.h>
 #include "common_util.h"
 #if defined(CONFIG_MIP405)
@@ -97,7 +97,7 @@ int get_boot_mode(void)
 {
        unsigned long pbcr;
        int res = 0;
-       pbcr = mfdcr (strap);
+       pbcr = mfdcr (CPC0_PSR);
        if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
                /* boot via MPS or MPS mapping */
                res = BOOT_MPS;
@@ -123,29 +123,29 @@ void setup_cs_reloc(void)
        /* first findout on which cs the flash is */
        if(mode & BOOT_MPS) {
                /* map flash high on CS1 and MPS on CS0 */
-               mtdcr (ebccfga, pb0ap);
-               mtdcr (ebccfgd, MPS_AP);
-               mtdcr (ebccfga, pb0cr);
-               mtdcr (ebccfgd, MPS_CR);
+               mtdcr (EBC0_CFGADDR, PB0AP);
+               mtdcr (EBC0_CFGDATA, MPS_AP);
+               mtdcr (EBC0_CFGADDR, PB0CR);
+               mtdcr (EBC0_CFGDATA, MPS_CR);
                /* we use the default values (max values) for the flash
                 * because its real size is not yet known */
-               mtdcr (ebccfga, pb1ap);
-               mtdcr (ebccfgd, FLASH_AP);
-               mtdcr (ebccfga, pb1cr);
-               mtdcr (ebccfgd, FLASH_CR_B);
+               mtdcr (EBC0_CFGADDR, PB1AP);
+               mtdcr (EBC0_CFGDATA, FLASH_AP);
+               mtdcr (EBC0_CFGADDR, PB1CR);
+               mtdcr (EBC0_CFGDATA, FLASH_CR_B);
        }
        else {
                /* map flash high on CS0 and MPS on CS1 */
-               mtdcr (ebccfga, pb1ap);
-               mtdcr (ebccfgd, MPS_AP);
-               mtdcr (ebccfga, pb1cr);
-               mtdcr (ebccfgd, MPS_CR);
+               mtdcr (EBC0_CFGADDR, PB1AP);
+               mtdcr (EBC0_CFGDATA, MPS_AP);
+               mtdcr (EBC0_CFGADDR, PB1CR);
+               mtdcr (EBC0_CFGDATA, MPS_CR);
                /* we use the default values (max values) for the flash
                 * because its real size is not yet known */
-               mtdcr (ebccfga, pb0ap);
-               mtdcr (ebccfgd, FLASH_AP);
-               mtdcr (ebccfga, pb0cr);
-               mtdcr (ebccfgd, FLASH_CR_B);
+               mtdcr (EBC0_CFGADDR, PB0AP);
+               mtdcr (EBC0_CFGDATA, FLASH_AP);
+               mtdcr (EBC0_CFGADDR, PB0CR);
+               mtdcr (EBC0_CFGDATA, FLASH_CR_B);
        }
 }
 
@@ -157,7 +157,7 @@ unsigned long flash_init (void)
        int i;
 
 #if !defined(CONFIG_PATI)
-       unsigned long size_b1,flashcr,size_reg;
+       unsigned long flashcr,size_reg;
        int mode;
        extern char version_string;
        char *p = &version_string;
@@ -197,7 +197,6 @@ unsigned long flash_init (void)
 #if !defined(CONFIG_PATI)
        /* protect reset vector */
        flash_info[0].protect[flash_info[0].sector_count-1] = 1;
-       size_b1 = 0 ;
        flash_info[0].size = size_b0;
        /* set up flash cs according to the size */
        size_reg=(flash_info[0].size >>20);
@@ -217,34 +216,34 @@ unsigned long flash_init (void)
        }
        if(mode & BOOT_MPS) {
                /* flash is on CS1 */
-               mtdcr(ebccfga, pb1cr);
-               flashcr = mfdcr (ebccfgd);
+               mtdcr(EBC0_CFGADDR, PB1CR);
+               flashcr = mfdcr (EBC0_CFGDATA);
                /* we map the flash high in every case */
                flashcr&=0x0001FFFF; /* mask out address bits */
                flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
                flashcr|= (i << 17); /* size addr */
-               mtdcr(ebccfga, pb1cr);
-               mtdcr(ebccfgd, flashcr);
+               mtdcr(EBC0_CFGADDR, PB1CR);
+               mtdcr(EBC0_CFGDATA, flashcr);
        }
        else {
                /* flash is on CS0 */
-               mtdcr(ebccfga, pb0cr);
-               flashcr = mfdcr (ebccfgd);
+               mtdcr(EBC0_CFGADDR, PB0CR);
+               flashcr = mfdcr (EBC0_CFGDATA);
                /* we map the flash high in every case */
                flashcr&=0x0001FFFF; /* mask out address bits */
                flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
                flashcr|= (i << 17); /* size addr */
-               mtdcr(ebccfga, pb0cr);
-               mtdcr(ebccfgd, flashcr);
+               mtdcr(EBC0_CFGADDR, PB0CR);
+               mtdcr(EBC0_CFGDATA, flashcr);
        }
 #if 0
        /* enable this (PIP405/MIP405 only) if you want to test if
           the relocation has be done ok.
           This will disable both Chipselects */
-       mtdcr (ebccfga, pb0cr);
-       mtdcr (ebccfgd, 0L);
-       mtdcr (ebccfga, pb1cr);
-       mtdcr (ebccfgd, 0L);
+       mtdcr (EBC0_CFGADDR, PB0CR);
+       mtdcr (EBC0_CFGDATA, 0L);
+       mtdcr (EBC0_CFGADDR, PB1CR);
+       mtdcr (EBC0_CFGDATA, 0L);
        printf("CS0 & CS1 switched off for test\n");
 #endif
        /* patch version_string */
@@ -600,7 +599,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
 {
        volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
        volatile FLASH_WORD_SIZE *addr2;
-       int flag, prot, sect, l_sect;
+       int flag, prot, sect;
        int i, rcode = 0;
 
 
@@ -632,8 +631,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
                printf ("\n");
        }
 
-       l_sect = -1;
-
        /* Disable interrupts which might cause a timeout here */
        flag = disable_interrupts();
 
@@ -672,7 +669,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
                                        rcode |= wait_for_DQ7(info, sect);
                                }
                        }
-                       l_sect = sect;
                        /*
                         * Wait for each sector to complete, it's more
                         * reliable.  According to AMD Spec, you must
@@ -691,16 +687,6 @@ int        flash_erase (flash_info_t *info, int s_first, int s_last)
        /* wait at least 80us - let's wait 1 ms */
        udelay (1000);
 
-#if 0
-       /*
-        * We wait for the last triggered sector
-        */
-       if (l_sect < 0)
-               goto DONE;
-       wait_for_DQ7(info, l_sect);
-
-DONE:
-#endif
        /* reset to read mode */
        addr = (FLASH_WORD_SIZE *)info->start[0];
        addr[0] = (FLASH_WORD_SIZE)0x00F000F0;  /* reset bank */
@@ -819,13 +805,17 @@ static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000;
 
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-       volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
-       volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
-       volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+       volatile FLASH_WORD_SIZE *addr2 = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+       volatile FLASH_WORD_SIZE *dest2 = (volatile FLASH_WORD_SIZE *)dest;
+       volatile FLASH_WORD_SIZE *data2;
        ulong start;
+       ulong *data_p;
        int flag;
        int i;
 
+       data_p = &data;
+       data2 = (volatile FLASH_WORD_SIZE *)data_p;
+
        /* Check if Flash is (sufficiently) erased */
        if ((*((volatile FLASH_WORD_SIZE *)dest) &
                (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {