Big white-space cleanup.

[karo-tx-uboot.git] / board / mpl / pip405 / pip405.h

diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index b41c5bb28274318ad7a9eb3eff181256603adbe0..5815786ebf74c97c6569143448c26be9f1a9bd54 100644 (file)
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -56,7 +56,7 @@ void user_led1(unsigned char on);
 /* timings */
 
 /* CS Config register (CS7) */
-#define CONFIG_PORT_BME        0       /* Burst disable */
+#define CONFIG_PORT_BME        0       /* Burst disable */
 #define CONFIG_PORT_TWE        255     /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
 #define CONFIG_PORT_CSN        1       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define CONFIG_PORT_OEN        1       /* Cycles from CS low to OE low   */
@@ -67,7 +67,7 @@ void user_led1(unsigned char on);
 #define CONFIG_PORT_SOR        1       /* Sample on Ready disabled */
 #define CONFIG_PORT_BEM        0       /* Byte Write only active on Write cycles */
 #define CONFIG_PORT_PEN        0       /* Parity disable */
-#define CONFIG_PORT_AP         ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
+#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
                                (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -80,10 +80,10 @@ void user_led1(unsigned char on);
 
 /* Flash CS0 or CS 1 */
 /* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B    1       /* Burst enable */
+#define FLASH_BME_B    1       /* Burst enable */
 #define FLASH_FWT_B    0x6     /* 6 * 30ns 210ns First Wait Access */
 #define FLASH_BWT_B    0x6     /* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME      0       /* Burst disable */
+#define FLASH_BME      0       /* Burst disable */
 #define FLASH_TWE      0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define FLASH_CSN      0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define FLASH_OEN      1       /* Cycles from CS low to OE low   */
@@ -95,10 +95,10 @@ void user_led1(unsigned char on);
 #define FLASH_BEM      0       /* Byte Write only active on Write cycles */
 #define FLASH_PEN      0       /* Parity disable */
 /* Access Parameter Register for non Boot */
-#define FLASH_AP       ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP       ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
                                (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 /* Access Parameter Register for Boot */
-#define FLASH_AP_B     ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
+#define FLASH_AP_B     ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
                                (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
@@ -114,10 +114,10 @@ void user_led1(unsigned char on);
 
 /* MPS CS1 or CS0 */
 /* Boot CS: */
-#define MPS_BME_B      1       /* Burst enable */
+#define MPS_BME_B      1       /* Burst enable */
 #define MPS_FWT_B      0x6/* 6 * 30ns 210ns First Wait Access */
 #define MPS_BWT_B      0x6     /* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME                0       /* Burst disable */
+#define MPS_BME                0       /* Burst disable */
 #define MPS_TWE                0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
 #define MPS_CSN                0       /* Chipselect is driven inactive for 1 Cycle BTW transfers */
 #define MPS_OEN                1       /* Cycles from CS low to OE low   */
@@ -129,10 +129,10 @@ void user_led1(unsigned char on);
 #define MPS_BEM                0       /* Byte Write only active on Write cycles */
 #define MPS_PEN                0       /* Parity disable */
 /* Access Parameter Register for non Boot */
-#define MPS_AP                 ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP         ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
                                (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 /* Access Parameter Register for Boot */
-#define MPS_AP_B       ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
+#define MPS_AP_B       ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
                                (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
 
 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */