/*
- *(C) Copyright 2005-2007 Netstal Maschinen AG
+ *(C) Copyright 2005-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* This source code is free software; you can redistribute it
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
-#include <asm/mmu.h>
+#include <asm/io.h>
+#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
-void sysLedSet(u32 value);
-
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
#undef BOOTSTRAP_OPTION_A_ACTIVE
#define SDR0_ECID2 0x0082
#define SDR0_ECID3 0x0083
-#define SYS_IO_ADDRESS 0xcce00000
-
-#define DEFAULT_ETH_ADDR "ethaddr"
-/* ethaddr for first or etha1ddr for second ethernet */
-
-enum {
- /* HW_GENERATION_HCU1 is no longer supported */
- HW_GENERATION_HCU2 = 0x10,
- HW_GENERATION_HCU3 = 0x10,
- HW_GENERATION_HCU4 = 0x20,
- HW_GENERATION_HCU5 = 0x30,
- HW_GENERATION_MCU = 0x08,
- HW_GENERATION_MCU20 = 0x0a,
- HW_GENERATION_MCU25 = 0x09,
-};
-
+#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000)
+#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000)
+#define HCU_SW_INSTALL_REQUESTED 0x10
/*
* This function is run very early, out of flash, and before devices are
int board_early_init_f(void)
{
- u32 reg;
#ifdef BOOTSTRAP_OPTION_A_ACTIVE
/* Booting with Bootstrap Option A
/*
* Initiate system reset in debug control register DBCR
*/
- dbcr = mfspr(dbcr0);
- mtspr(dbcr0, dbcr | CHIP_RESET);
+ dbcr = mfspr(SPRN_DBCR0);
+ mtspr(SPRN_DBCR0, dbcr | CHIP_RESET);
}
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
#endif
- mtdcr(ebccfga, xbcfg);
- mtdcr(ebccfgd, 0xb8400000);
+ mtdcr(EBC0_CFGADDR, EBC0_CFG);
+ mtdcr(EBC0_CFGDATA, 0xb8400000);
- /*--------------------------------------------------------------------
+ /*
* Setup the GPIO pins
- *-------------------------------------------------------------------*/
- /* test-only: take GPIO init from pcs440ep ???? in config file */
+ */
out32(GPIO0_OR, 0x00000000);
out32(GPIO0_TCR, 0x7C2FF1CF);
out32(GPIO0_OSRL, 0x40055000);
out32(GPIO1_ISR3L, 0x00000000);
out32(GPIO1_ISR3H, 0x00000000);
- /*--------------------------------------------------------------------
+ /*
* Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
- mtdcr(uic0sr, 0xffffffff); /* clear all */
- mtdcr(uic0er, 0x00000000); /* disable all */
- mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
- mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic0sr, 0xffffffff); /* clear all */
-
- mtdcr(uic1sr, 0xffffffff); /* clear all */
- mtdcr(uic1er, 0x00000000); /* disable all */
- mtdcr(uic1cr, 0x00000000); /* all non-critical */
- mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic1sr, 0xffffffff); /* clear all */
-
- mtdcr(uic2sr, 0xffffffff); /* clear all */
- mtdcr(uic2er, 0x00000000); /* disable all */
- mtdcr(uic2cr, 0x00000000); /* all non-critical */
- mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
- mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
- mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(uic2sr, 0xffffffff); /* clear all */
- mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
- mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
-
- /* PCI arbiter enabled */
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg);
-
- pci_pre_init(0);
+ */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+ mtdcr(UIC0ER, 0x00000000); /* disable all */
+ mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
+ mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
+ mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC0SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+ mtdcr(UIC1ER, 0x00000000); /* disable all */
+ mtdcr(UIC1CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtdcr(UIC2ER, 0x00000000); /* disable all */
+ mtdcr(UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
+ mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
+ mtdcr(UIC2SR, 0xffffffff); /* clear all */
+ mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */
+ mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */
/* setup BOOT FLASH */
mtsdr(SDR0_CUST0, 0xC0082350);
return 0;
}
+#ifdef CONFIG_BOARD_PRE_INIT
int board_pre_init(void)
{
return board_early_init_f();
}
+#endif
+
+int sys_install_requested(void)
+{
+ u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
+ return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
+}
+
int checkboard(void)
{
- unsigned int j;
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
- u16 generation = *boardVersReg & 0xf0;
- u16 index = *boardVersReg & 0x0f;
+ u16 generation = in_be16(boardVersReg) & 0xf0;
+ u16 index = in_be16(boardVersReg) & 0x0f;
u32 ecid0, ecid1, ecid2, ecid3;
- printf("Netstal Maschinen AG: ");
- if (generation == HW_GENERATION_HCU3)
- printf("HCU3: index %d", index);
- else if (generation == HW_GENERATION_HCU4)
- printf("HCU4: index %d", index);
- else if (generation == HW_GENERATION_HCU5)
- printf("HCU5: index %d", index);
- printf(" HW 0x%02x\n", *hwVersReg & 0xff);
+ nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
mfsdr(SDR0_ECID0, ecid0);
mfsdr(SDR0_ECID1, ecid1);
mfsdr(SDR0_ECID2, ecid2);
mfsdr(SDR0_ECID3, ecid3);
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
- for (j = 0;j < 6; j++) {
- sysLedSet(1 << j);
- udelay(200 * 1000);
- }
return 0;
}
-u32 sysLedGet(void)
+u32 hcu_led_get(void)
{
return in16(SYS_IO_ADDRESS) & 0x3f;
}
-void sysLedSet(u32 value /* value to place in LEDs */)
+/*
+ * hcu_led_set value to be placed into the LEDs (max 6 bit)
+ */
+void hcu_led_set(u32 value)
{
out16(SYS_IO_ADDRESS, value);
}
-/*---------------------------------------------------------------------------+
- * getSerialNr
- *---------------------------------------------------------------------------*/
-static u32 getSerialNr(void)
+/*
+ * get_serial_number
+ */
+u32 get_serial_number(void)
{
- u32 *serial = (u32 *)CFG_FLASH_BASE;
+ u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
+
+ if (in_be32(serial) == 0xffffffff)
+ return 0;
+
+ return in_be32(serial);
+}
- if (*serial == 0xffffffff)
- return get_ticks();
- return *serial;
+/*
+ * hcu_get_slot
+ */
+u32 hcu_get_slot(void)
+{
+ u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
+ return in_be16(slot) & 0x7f;
}
-/*---------------------------------------------------------------------------+
+/*
* misc_init_r.
- *---------------------------------------------------------------------------*/
+ */
int misc_init_r(void)
{
- char *s = getenv(DEFAULT_ETH_ADDR);
- char *e;
- int i;
- u32 serial = getSerialNr();
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
- for (i = 0; i < 6; ++i) {
- gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
- if (s)
- s = (*e) ? e + 1 : e;
- }
-
- if (gd->bd->bi_enetaddr[3] == 0 &&
- gd->bd->bi_enetaddr[4] == 0 &&
- gd->bd->bi_enetaddr[5] == 0) {
- char ethaddr[22];
-
- /* Must be in sync with CONFIG_ETHADDR */
- gd->bd->bi_enetaddr[0] = 0x00;
- gd->bd->bi_enetaddr[1] = 0x60;
- gd->bd->bi_enetaddr[2] = 0x13;
- gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
- gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
- /* byte[5].bit 0 must be zero */
- gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
- sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
- gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
- gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
- gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
- printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
- ethaddr, serial);
- setenv(DEFAULT_ETH_ADDR, ethaddr);
- }
-
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
+#ifdef CONFIG_ENV_ADDR_REDUND
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
+#endif
#endif
/*
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative
- when connecting the Device to the PHY */
+ * when connecting the Device to the PHY
+ */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
mtsdr(SDR0_SRST1, 0x00000000);
udelay(1000);
mtsdr(SDR0_SRST0, 0x00000000);
-
printf("USB: Host(int phy) Device(ext phy)\n");
+ common_misc_init_r();
+ set_params_for_sw_install( sys_install_requested(), "hcu5" );
+ /* We cannot easily enable trace before, as there are other
+ * routines messing around with sdr0_pfc1. And I do not need it.
+ */
+ if (mfspr(SPRN_DBCR0) & 0x80000000) {
+ /* External debugger alive
+ * enable trace facilty for Lauterbach
+ * CCR0[DTB]=0 Enable broadcast of trace information
+ * SDR0_PFC0[TRE] Trace signals are enabled instead of
+ * GPIO49-63
+ */
+ mtspr(SPRN_CCR0, mfspr(SPRN_CCR0) &~ (CCR0_DTB));
+ mtsdr(SDR0_PFC0, sdr0_pfc1 | SDR0_PFC0_TRE_ENABLE);
+ }
return 0;
}
+#ifdef CONFIG_PCI
+int board_with_pci(void)
+{
+ u32 reg;
-/*************************************************************************
+ mfsdr(SDR0_PCI0, reg);
+ return (reg & SDR0_XCR_PAE_MASK);
+}
+
+/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
- ************************************************************************/
-#if defined(CONFIG_PCI)
+ */
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
- /*-------------------------------------------------------------------+
+ if (!board_with_pci()) { return 0; }
+
+ /*
+ * Set priority for all PLB3 devices to 0.
+ * Set PLB3 arbiter to fair mode.
+ */
+ mfsdr(SD0_AMP1, addr);
+ mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB3_ACR);
+ mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
+
+ /*
+ * Set priority for all PLB4 devices to 0.
+ */
+ mfsdr(SD0_AMP0, addr);
+ mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(PLB4_ACR, addr); /* Sequoia */
+
+ /*
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
* Workaround: Disable write pipelining to DDR SDRAM by setting
* PLB0_ACR[WRP] = 0.
- *-------------------------------------------------------------------*/
-
- /*-------------------------------------------------------------------+
- | Set priority for all PLB3 devices to 0.
- | Set PLB3 arbiter to fair mode.
- +-------------------------------------------------------------------*/
- mfsdr(sdr_amp1, addr);
- mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb3_acr);
- /* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
- mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
-
- /*-------------------------------------------------------------------+
- | Set priority for all PLB4 devices to 0.
- +-------------------------------------------------------------------*/
- mfsdr(sdr_amp0, addr);
- mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
- /* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
- mtdcr(plb4_acr, addr); /* Sequoia */
-
- /*-------------------------------------------------------------------+
- | Set Nebula PLB4 arbiter to fair mode.
- +-------------------------------------------------------------------*/
- /* Segment0 */
- addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
- addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
- addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
- /* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
- addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
-
- /* mtdcr(plb0_acr, addr); */ /* Sequoia */
- mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+ */
+ mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */
- addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
- addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
- addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
- addr = (addr & ~plb1_acr_wrp_mask) ;
- /* mtdcr(plb1_acr, addr); */ /* Sequoia */
- mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
+ mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */
- return 1;
+ return board_with_pci();
}
-#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
+/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+ */
void pci_target_init(struct pci_controller *hose)
{
- /*-------------------------------------------------------------+
+ if (!board_with_pci()) { return; }
+ /*
* Set up Direct MMIO registers
- *-------------------------------------------------------------*/
- /*-------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
- | 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +-------------------------------------------------------------*/
+ *
+ * PowerPC440EPX PCI Master configuration.
+ * Map one 1Gig range of PLB/processor addresses to PCI memory space.
+ * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
+ * 0xA0000000-0xDFFFFFFF
+ * Use byte reversed out routines to handle endianess.
+ * Make this region non-prefetchable.
+ */
/* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM0MA, 0x00000000);
- out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIL0_PMM0MA, 0x00000000);
+ out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
/* PMM0 PCI Low Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
- out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+ out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM0MA, 0xE0000001);
+ out32r(PCIL0_PMM0MA, 0xE0000001);
/* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIX0_PMM1MA, 0x00000000);
- out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIL0_PMM1MA, 0x00000000);
+ out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
/* PMM0 PCI Low Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
- out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
+ out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+ out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
/* 512M + No prefetching, and enable region */
- out32r(PCIX0_PMM1MA, 0xE0000001);
+ out32r(PCIL0_PMM1MA, 0xE0000001);
- out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
+ out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
+ out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
- /*------------------------------------------------------------------+
+ /*
* Set up Configuration registers
- *------------------------------------------------------------------*/
+ */
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CFG_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+ CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-/*************************************************************************
+/*
* pci_master_init
*
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+ */
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
+ if (!board_with_pci()) { return; }
- /*---------------------------------------------------------------+
- | Write the PowerPC440 EP PCI Configuration regs.
- | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
- | Enable PowerPC440 EP to act as a PCI memory target (PTM).
- +--------------------------------------------------------------*/
+ /*---------------------------------------------------------------
+ * Write the PowerPC440 EP PCI Configuration regs.
+ * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+ * Enable PowerPC440 EP to act as a PCI memory target (PTM).
+ *--------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif
-/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
-/*************************************************************************
+/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
+ */
int is_pci_host(struct pci_controller *hose)
{
return 1;
}
-#endif /* defined(CONFIG_PCI) */
+#endif /* defined(CONFIG_PCI) */
+
+#if defined(CONFIG_POST)
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+#endif /* CONFIG_POST */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29F040 flash, 8 bit flash / 8 bit bus.
+ */
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = 1;
+ info->chipwidth = 1;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
projects / karo-tx-uboot.git / blobdiff