Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / netstal / hcu5 / hcu5.c

diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 5eb33d37fac1dc800d22d0132b0430fc3b4d1c89..946c3f3a4dd304a97e6b7a727241db3b84178f4a 100644 (file)
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -94,8 +94,8 @@ int board_early_init_f(void)
        }
        mtsdr(SDR0_CP440, 0x0EAAEA02);  /* [Nto1] = 1*/
 #endif
-       mtdcr(ebccfga, xbcfg);
-       mtdcr(ebccfgd, 0xb8400000);
+       mtdcr(EBC0_CFGADDR, EBC0_CFG);
+       mtdcr(EBC0_CFGDATA, 0xb8400000);
 
        /*
         * Setup the GPIO pins
@@ -129,31 +129,31 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtsdr(sdr_pfc0, 0x00003E00);    /* Pin function:  */
-       mtsdr(sdr_pfc1, 0x00848000);    /* Pin function: UART0 has 4 pins */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtsdr(SDR0_PFC0, 0x00003E00);   /* Pin function:  */
+       mtsdr(SDR0_PFC1, 0x00848000);   /* Pin function: UART0 has 4 pins */
 
        /* setup BOOT FLASH */
        mtsdr(SDR0_CUST0, 0xC0082350);
@@ -324,7 +324,7 @@ int board_with_pci(void)
 {
        u32 reg;
 
-       mfsdr(sdr_pci0, reg);
+       mfsdr(SDR0_PCI0, reg);
        return (reg & SDR0_XCR_PAE_MASK);
 }
 
@@ -350,28 +350,28 @@ int pci_pre_init(struct pci_controller *hose)
         * Set priority for all PLB3 devices to 0.
         * Set PLB3 arbiter to fair mode.
         */
-       mfsdr(sdr_amp1, addr);
-       mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb3_acr);
-       mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
+       mfsdr(SD0_AMP1, addr);
+       mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB3_ACR);
+       mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */
 
        /*
         * Set priority for all PLB4 devices to 0.
         */
-       mfsdr(sdr_amp0, addr);
-       mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
-       addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
-       mtdcr(plb4_acr, addr);  /* Sequoia */
+       mfsdr(SD0_AMP0, addr);
+       mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+       addr = mfdcr(PLB4_ACR) | 0xa0000000;    /* Was 0x8---- */
+       mtdcr(PLB4_ACR, addr);  /* Sequoia */
 
        /*
         * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
         * Workaround: Disable write pipelining to DDR SDRAM by setting
         * PLB0_ACR[WRP] = 0.
         */
-       mtdcr(plb0_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+       mtdcr(PLB0_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 
        /* Segment1 */
-       mtdcr(plb1_acr, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
+       mtdcr(PLB1_ACR, 0);  /* PATCH HAB: WRITE PIPELINING OFF */
 
        return board_with_pci();
 }
@@ -398,27 +398,27 @@ void pci_target_init(struct pci_controller *hose)
         * Make this region non-prefetchable.
         */
        /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0MA, 0x00000000);
-       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIL0_PMM0MA, 0x00000000);
+       out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
-       out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
+       out32r(PCIL0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        /* 512M + No prefetching, and enable region */
-       out32r(PCIX0_PMM0MA, 0xE0000001);
+       out32r(PCIL0_PMM0MA, 0xE0000001);
 
        /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1MA, 0x00000000);
-       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIL0_PMM1MA, 0x00000000);
+       out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
        /* PMM0 PCI Low Address */
-       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
-       out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
+       out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
+       out32r(PCIL0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        /* 512M + No prefetching, and enable region */
-       out32r(PCIX0_PMM1MA, 0xE0000001);
+       out32r(PCIL0_PMM1MA, 0xE0000001);
 
-       out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
-       out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
-       out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
-       out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
+       out32r(PCIL0_PTM1LA, 0);        /* Local Addr. Reg */
+       out32r(PCIL0_PTM2MS, 0);        /* Memory Size/Attribute */
+       out32r(PCIL0_PTM2LA, 0);        /* Local Addr. Reg */
 
        /*
         * Set up Configuration registers