ARM: AM33xx: Cleanup dplls data

[karo-tx-uboot.git] / board / phytec / pcm051 / board.c

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 43d7b6e15ac87c0173618048f7febb6092266c04..17a98ff860097dae95bfe6fa679dbe4c444a27da 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -6,15 +6,7 @@
  * Copyright (C) 2013 Lemonage Software GmbH
  * Author Lars Poeschel <poeschel@lemonage.de>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -39,9 +31,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -50,29 +39,18 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 /* DDR RAM defines */
 #define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+               DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
 
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+       return &dpll_ddr;
 }
 
 static const struct ddr_data ddr3_data = {
@@ -114,6 +92,15 @@ static struct emif_regs ddr3_emif_reg_data = {
  */
 void s_init(void)
 {
+       /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
+
        /*
         * WDT1 is already running when the bootloader gets control
         * Disable it to avoid "random" resets
@@ -132,22 +119,8 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
-
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
-               != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;