Merge branch 'u-boot/master' into u-boot-arm/master

[karo-tx-uboot.git] / board / quad100hd / nand.c

diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c
index a36b89dd79dabf2cd3a98832971df4eea679a809..47bbb6b262394b601fa136f5ca1bad0548be623a 100644 (file)
--- a/board/quad100hd/nand.c
+++ b/board/quad100hd/nand.c
@@ -2,63 +2,37 @@
  * (C) Copyright 2008
  * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <config.h>
 #if defined(CONFIG_CMD_NAND)
-#include <asm/gpio.h>
+#include <asm/ppc4xx-gpio.h>
+#include <asm/io.h>
 #include <nand.h>
 
 /*
  *     hardware specific access to control-lines
  */
-static void quad100hd_hwcontrol(struct mtd_info *mtd, int cmd)
+static void quad100hd_hwcontrol(struct mtd_info *mtd,
+                               int cmd, unsigned int ctrl)
 {
-       switch(cmd) {
-       case NAND_CTL_SETCLE:
-               gpio_write_bit(CFG_NAND_CLE, 1);
-               break;
-       case NAND_CTL_CLRCLE:
-               gpio_write_bit(CFG_NAND_CLE, 0);
-               break;
+       struct nand_chip *this = mtd->priv;
 
-       case NAND_CTL_SETALE:
-               gpio_write_bit(CFG_NAND_ALE, 1);
-               break;
-       case NAND_CTL_CLRALE:
-               gpio_write_bit(CFG_NAND_ALE, 0);
-               break;
-
-       case NAND_CTL_SETNCE:
-               gpio_write_bit(CFG_NAND_CE, 0);
-               break;
-       case NAND_CTL_CLRNCE:
-               gpio_write_bit(CFG_NAND_CE, 1);
-               break;
+       if (ctrl & NAND_CTRL_CHANGE) {
+               gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
+               gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
+               gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
        }
+
+       if (cmd != NAND_CMD_NONE)
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 static int quad100hd_nand_ready(struct mtd_info *mtd)
 {
-       return gpio_read_in_bit(CFG_NAND_RDY);
+       return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
 }
 
 /*
@@ -67,9 +41,9 @@ static int quad100hd_nand_ready(struct mtd_info *mtd)
 int board_nand_init(struct nand_chip *nand)
 {
        /* Set address of hardware control function */
-       nand->hwcontrol = quad100hd_hwcontrol;
+       nand->cmd_ctrl = quad100hd_hwcontrol;
        nand->dev_ready = quad100hd_nand_ready;
-       nand->eccmode = NAND_ECC_SOFT;
+       nand->ecc.mode = NAND_ECC_SOFT;
        /* 15 us command delay time */
        nand->chip_delay =  20;