Merge branch 'master' of git://www.denx.de/git/u-boot-imx

[karo-tx-uboot.git] / board / sunxi / gmac.c

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e7ff95285c97be8e816e2c31a8e739dd91c861db..571bc9e0ab0d49ba3ab6c1ef621adff2f038441e 100644 (file)
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -13,7 +13,12 @@ int sunxi_gmac_initialize(bd_t *bis)
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
        /* Set up clock gating */
+#ifndef CONFIG_MACH_SUN6I
        setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+       setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
+       setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#endif
 
        /* Set MII clock */
 #ifdef CONFIG_RGMII
@@ -24,6 +29,16 @@ int sunxi_gmac_initialize(bd_t *bis)
                CCM_GMAC_CTRL_GPIT_MII);
 #endif
 
+       /*
+        * In order for the gmac nic to work reliable on the Bananapi, we
+        * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
+        * of the GMAC clk register to 3.
+        */
+#ifdef CONFIG_TARGET_BANANAPI
+       setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
+#endif
+
+#ifndef CONFIG_MACH_SUN6I
        /* Configure pin mux settings for GMAC */
        for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
 #ifdef CONFIG_RGMII
@@ -34,9 +49,48 @@ int sunxi_gmac_initialize(bd_t *bis)
                sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
                sunxi_gpio_set_drv(pin, 3);
        }
+#elif defined CONFIG_RGMII
+       /* Configure sun6i RGMII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+       for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 3);
+       }
+#elif defined CONFIG_GMII
+       /* Configure sun6i GMII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+               sunxi_gpio_set_drv(pin, 2);
+       }
+#else
+       /* Configure sun6i MII mode pin mux settings */
+       for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+       for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
+               sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC);
+#endif
 
 #ifdef CONFIG_RGMII
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#elif defined CONFIG_GMII
+       return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII);
 #else
        return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
 #endif