Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[karo-tx-uboot.git] / board / ti / am335x / board.c

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index b371376bc72c0f6d0b5c6118057065a6cd1679e4..fdbe26cde116b81e0bf7e1c41d233cd3d36e5f87 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,9 +38,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -126,28 +123,7 @@ static int read_eeprom(void)
        return 0;
 }
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr2_data = {
        .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
                          (MT47H128M16RT25E_RD_DQS<<20) |
@@ -297,6 +273,15 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
        .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
                                PHY_EN_DYN_PWRDN,
 };
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+       /* break into full u-boot on 'c' */
+       return (serial_tstc() && serial_getc() == 'c');
+}
+#endif
+
 #endif
 
 /*
@@ -304,6 +289,15 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
  */
 void s_init(void)
 {
+       /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
+
        /* WDT1 is already running when the bootloader gets control
         * Disable it to avoid "random" resets
         */
@@ -321,9 +315,6 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regVal;
-
 #ifdef CONFIG_SERIAL1
        enable_uart0_pin_mux();
 #endif /* CONFIG_SERIAL1 */
@@ -343,17 +334,7 @@ void s_init(void)
        enable_uart5_pin_mux();
 #endif /* CONFIG_SERIAL6 */
 
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_RESET;
-       writel(regVal, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_SMART_IDLE_EN;
-       writel(regVal, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;
 
@@ -496,6 +477,7 @@ int board_eth_init(bd_t *bis)
                        eth_setenv_enetaddr("ethaddr", mac_addr);
        }
 
+#ifdef CONFIG_DRIVER_TI_CPSW
        if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
                writel(MII_MODE_ENABLE, &cdev->miisel);
                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -511,6 +493,7 @@ int board_eth_init(bd_t *bis)
                printf("Error %d registering CPSW switch\n", rv);
        else
                n += rv;
+#endif
 
        /*
         *