Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / board / ti / am335x / mux.c

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 02837082cb807fad040f8c4007c7bb7d218cdbfc..b2bfda5ea9f60a8214ee93e88ae3a842d944cae0 100644 (file)
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -190,6 +190,75 @@ static struct module_pin_mux nand_pin_mux[] = {
        {-1},
 };
 
+#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux bone_norcape_pin_mux[] = {
+       {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A0 */
+       {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A1 */
+       {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A2 */
+       {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A3 */
+       {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A4 */
+       {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A5 */
+       {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A6 */
+       {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A7 */
+       {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A8 */
+       {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A9 */
+       {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE},       /* NOR_A10 */
+       {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
+       {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A12 */
+       {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE},     /* NOR_A13 */
+       {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A14 */
+       {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A15 */
+       {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A16 */
+       {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A17 */
+       {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A18 */
+       {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE},    /* NOR_A19 */
+       {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD0 */
+       {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD1 */
+       {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD2 */
+       {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD3 */
+       {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD4 */
+       {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD5 */
+       {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD6 */
+       {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD7 */
+       {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD8 */
+       {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE},      /* NOR_AD9 */
+       {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD10 */
+       {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD11 */
+       {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD12 */
+       {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD13 */
+       {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD14 */
+       {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE},     /* NOR_AD15 */
+
+       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE},   /* NOR_CE */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
+       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
+       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)},    /* NOR_WEN */
+       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
+       {-1},
+};
+#endif
+
+#if defined(CONFIG_NOR_BOOT)
+static struct module_pin_mux norboot_pin_mux[] = {
+       {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
+       {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
+       {-1},
+};
+
+void enable_norboot_pin_mux(void)
+{
+       configure_module_pin_mux(norboot_pin_mux);
+}
+#endif
+
 void enable_uart0_pin_mux(void)
 {
        configure_module_pin_mux(uart0_pin_mux);
@@ -262,13 +331,18 @@ static unsigned short detect_daughter_board_profile(void)
 void enable_board_pin_mux(struct am335x_baseboard_id *header)
 {
        /* Do board-specific muxes. */
-       if (!strncmp(header->name, "A335BONE", HDR_NAME_LEN)) {
+       if (board_is_bone(header)) {
                /* Beaglebone pinmux */
                configure_module_pin_mux(i2c1_pin_mux);
                configure_module_pin_mux(mii1_pin_mux);
                configure_module_pin_mux(mmc0_pin_mux);
+#ifndef CONFIG_NOR
                configure_module_pin_mux(mmc1_pin_mux);
-       } else if (!strncmp(header->config, "SKU#01", 6)) {
+#endif
+#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
+               configure_module_pin_mux(bone_norcape_pin_mux);
+#endif
+       } else if (board_is_gp_evm(header)) {
                /* General Purpose EVM */
                unsigned short profile = detect_daughter_board_profile();
                configure_module_pin_mux(rgmii1_pin_mux);
@@ -283,7 +357,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                        configure_module_pin_mux(mmc1_pin_mux);
                        configure_module_pin_mux(spi0_pin_mux);
                }
-       } else if (!strncmp(header->config, "SKU#02", 6)) {
+       } else if (board_is_idk(header)) {
                /*
                 * Industrial Motor Control (IDK)
                 * note: IDK console is on UART3 by default.
@@ -292,13 +366,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                 */
                configure_module_pin_mux(mii1_pin_mux);
                configure_module_pin_mux(mmc0_no_cd_pin_mux);
-       } else if (!strncmp(header->name, "A335X_SK", HDR_NAME_LEN)) {
+       } else if (board_is_evm_sk(header)) {
                /* Starter Kit EVM */
                configure_module_pin_mux(i2c1_pin_mux);
                configure_module_pin_mux(gpio0_7_pin_mux);
                configure_module_pin_mux(rgmii1_pin_mux);
                configure_module_pin_mux(mmc0_pin_mux_sk_evm);
-       } else if (!strncmp(header->name, "A335BNLT", HDR_NAME_LEN)) {
+       } else if (board_is_bone_lt(header)) {
                /* Beaglebone LT pinmux */
                configure_module_pin_mux(i2c1_pin_mux);
                configure_module_pin_mux(mii1_pin_mux);