* Syed Mohammed Khasim <khasim@ti.com>
*
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_STATUS_LED
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
+#include <asm/omap_musb.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
#include "beagle.h"
#include <command.h>
#define BBTOYS_LCD 0x03000B00
#define BCT_BRETTL3 0x01000F00
#define BCT_BRETTL4 0x02000F00
+#define LSR_COM6L_ADPT 0x01001300
#define BEAGLE_NO_EEPROM 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
/*
* Routine: get_board_revision
* Description: Detect if we are running on a Beagle revision Ax/Bx,
- * C1/2/3, C4 or xM. This can be done by reading
+ * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading
* the level of GPIO173, GPIO172 and GPIO171. This should
* result in
* GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
* GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
- * GPIO173, GPIO172, GPIO171: 0 0 0 => xM
+ * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx
+ * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx
*/
static int get_board_revision(void)
{
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
{
int pop_mfr, pop_id;
*/
identify_nand_chip(&pop_mfr, &pop_id);
- *mr = MICRON_V_MR_165;
+ timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
}
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
if (pop_mfr == 0) {
/* 256MB DDR */
- *mcfg = MICRON_V_MCFG_200(256 << 20);
- *ctrla = MICRON_V_ACTIMA_200;
- *ctrlb = MICRON_V_ACTIMB_200;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
} else {
/* 512MB DDR */
- *mcfg = NUMONYX_V_MCFG_165(512 << 20);
- *ctrla = NUMONYX_V_ACTIMA_165;
- *ctrlb = NUMONYX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
- *mcfg = MICRON_V_MCFG_165(128 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}
#endif
i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
sizeof(expansion_config));
+ /* retry reading configuration data with 16bit addressing */
+ if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+ (expansion_config.device_vendor == 0xFFFFFFFF)) {
+ printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+ }
+
i2c_set_bus_num(TWL4030_I2C_BUS);
return expansion_config.device_vendor;
case REVISION_C4:
omap3_dss_panel_config(&dvid_cfg);
break;
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
default:
omap3_dss_panel_config(&dvid_cfg_xm);
case REVISION_AXBX:
case REVISION_CX:
case REVISION_C4:
- case REVISION_XM_A:
gpio_request(170, "");
gpio_direction_output(170, 0);
gpio_set_value(170, 1);
break;
- case REVISION_XM_B:
+ case REVISION_XM_AB:
case REVISION_XM_C:
default:
#define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
}
#endif
+#ifdef CONFIG_USB_MUSB_OMAP2PLUS
+static struct musb_hdrc_config musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &musb_config,
+ .power = 100,
+ .platform_ops = &omap2430_ops,
+ .board_data = &musb_board_data,
+};
+#endif
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
+ bool generate_fake_mac = false;
/* Enable i2c2 pullup resisters */
writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
break;
- case REVISION_XM_A:
- printf("Beagle xM Rev A\n");
- setenv("beaglerev", "xMA");
- MUX_BEAGLE_XM();
- /* Set VAUX2 to 1.8V for EHCI PHY */
- twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
- TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
- TWL4030_PM_RECEIVER_DEV_GRP_P1);
- break;
- case REVISION_XM_B:
- printf("Beagle xM Rev B\n");
- setenv("beaglerev", "xMB");
+ case REVISION_XM_AB:
+ printf("Beagle xM Rev A/B\n");
+ setenv("beaglerev", "xMAB");
MUX_BEAGLE_XM();
/* Set VAUX2 to 1.8V for EHCI PHY */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
case REVISION_XM_C:
printf("Beagle xM Rev C\n");
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
break;
default:
printf("Beagle unknown 0x%02x\n", get_board_revision());
TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+ generate_fake_mac = true;
}
switch (get_expansion_id()) {
case BCT_BRETTL4:
printf("Recognized bct electronic GmbH brettl4 board\n");
break;
+ case LSR_COM6L_ADPT:
+ printf("Recognized LSR COM6L Adapter Board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "lsr-com6l-adpt");
+ break;
case BEAGLE_NO_EEPROM:
printf("No EEPROM on expansion board\n");
setenv("buddy", "none");
twl4030_power_init();
switch (get_board_revision()) {
- case REVISION_XM_A:
- case REVISION_XM_B:
+ case REVISION_XM_AB:
twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
break;
default:
omap3_dss_enable();
#endif
+#ifdef CONFIG_USB_MUSB_OMAP2PLUS
+ musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
+#endif
+
+ if (generate_fake_mac) {
+ u32 id[4];
+
+ get_dieid(id);
+ usb_fake_mac_from_die_id(id);
+ }
+
return 0;
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
/* Call usb_stop() before starting the kernel */
void show_boot_progress(int val)
{
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI */
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)
+int board_eth_init(bd_t *bis)
+{
+ return usb_eth_initialize(bis);
+}
+#endif
projects / karo-tx-uboot.git / blobdiff