#include <usb.h>
#include <asm/omap_common.h>
#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
#include <asm/arch/clock.h>
+#include <asm/arch/dra7xx_iodelay.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/omap.h>
#include <environment.h>
+#include <usb.h>
+#include <linux/usb/gadget.h>
+#include <dwc3-uboot.h>
+#include <dwc3-omap-uboot.h>
+#include <ti-usb-phy-uboot.h>
#include "mux_data.h"
DECLARE_GLOBAL_DATA_PTR;
+/* GPIO 7_11 */
+#define GPIO_DDR_VTT_EN 203
+
const struct omap_sysinfo sysinfo = {
"Board: BeagleBoard x15\n"
};
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
+/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00740074,
+ 0x00780078,
+ 0x007c007c,
+ 0x007b007b,
0x00800080,
0x00360036,
0x00340034,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
- .read_idle_ctrl = 0x00050001,
+ .read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0e24400a,
- .emif_ddr_phy_ctlr_1 = 0x0e24400a,
+ .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+ .emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00820082,
+ 0x008b008b,
+ 0x00800080,
+ 0x007e007e,
0x00800080,
0x00370037,
0x00390039,
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
- 0x00400040
+ 0x00400040,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0,
+ 0x0
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
return 0;
}
-static void do_set_mux32(u32 base,
- struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_essential(void)
{
- int i;
- struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
-
- for (i = 0; i < size; i++, pad++)
- writel(pad->val, base + pad->offset);
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ early_padconf, ARRAY_SIZE(early_padconf));
}
-void set_muxconf_regs_essential(void)
+#ifdef CONFIG_IODELAY_RECALIBRATION
+void recalibrate_iodelay(void)
{
- do_set_mux32((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
+ __recalibrate_iodelay(core_padconf_array_essential,
+ ARRAY_SIZE(core_padconf_array_essential),
+ iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
}
+#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device usb_otg_ss1 = {
+ .maximum_speed = USB_SPEED_SUPER,
+ .base = DRA7_USB_OTG_SS1_BASE,
+ .tx_fifo_resize = false,
+ .index = 0,
+};
+
+static struct dwc3_omap_device usb_otg_ss1_glue = {
+ .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
+ .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+ .index = 0,
+};
+
+static struct ti_usb_phy_device usb_phy1_device = {
+ .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
+ .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
+ .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
+ .index = 0,
+};
+
+static struct dwc3_device usb_otg_ss2 = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = DRA7_USB_OTG_SS2_BASE,
+ .tx_fifo_resize = false,
+ .index = 1,
+};
+
+static struct dwc3_omap_device usb_otg_ss2_glue = {
+ .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
+ .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
+ .index = 1,
+};
+
+static struct ti_usb_phy_device usb_phy2_device = {
+ .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
+ .index = 1,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ enable_usb_clocks(index);
+ switch (index) {
+ case 0:
+ if (init == USB_INIT_DEVICE) {
+ printf("port %d can't be used as device\n", index);
+ disable_usb_clocks(index);
+ return -EINVAL;
+ } else {
+ usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
+ usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+ setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
+ OTG_SS_CLKCTRL_MODULEMODE_HW |
+ OPTFCLKEN_REFCLK960M);
+ }
+
+ ti_usb_phy_uboot_init(&usb_phy1_device);
+ dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+ dwc3_uboot_init(&usb_otg_ss1);
+ break;
+ case 1:
+ if (init == USB_INIT_DEVICE) {
+ usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
+ usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+ } else {
+ printf("port %d can't be used as host\n", index);
+ disable_usb_clocks(index);
+ return -EINVAL;
+ }
+
+ ti_usb_phy_uboot_init(&usb_phy2_device);
+ dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+ dwc3_uboot_init(&usb_otg_ss2);
+ break;
+ default:
+ printf("Invalid Controller Index\n");
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ switch (index) {
+ case 0:
+ case 1:
+ ti_usb_phy_uboot_exit(index);
+ dwc3_uboot_exit(index);
+ dwc3_omap_uboot_exit(index);
+ break;
+ default:
+ printf("Invalid Controller Index\n");
+ }
+ disable_usb_clocks(index);
+ return 0;
+}
+
+int usb_gadget_handle_interrupts(int index)
+{
+ u32 status;
+
+ status = dwc3_omap_uboot_interrupt_status(index);
+ if (status)
+ dwc3_uboot_handle_interrupt(index);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_DRIVER_TI_CPSW
/* Delay value to add to calibrated value */
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
- if (is_valid_ether_addr(mac_addr))
+ if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
mac_addr[5] = mac_lo & 0xFF;
if (!getenv("eth1addr")) {
- if (is_valid_ether_addr(mac_addr))
+ if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
}
#endif
-#ifdef CONFIG_USB_XHCI_OMAP
-int board_usb_init(int index, enum usb_init_type init)
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+/* VTT regulator enable */
+static inline void vtt_regulator_enable(void)
{
- setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,
- OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);
+ if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
+ return;
+ gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+ gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+}
+
+int board_early_init_f(void)
+{
+ vtt_regulator_enable();
return 0;
}
#endif
projects / karo-tx-uboot.git / blobdiff