#include <asm/arch/iomux.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
#include <i2c.h>
#include <mmc.h>
+#include <pmic.h>
#include <fsl_esdhc.h>
#include <fsl_pmic.h>
#include <mc13892.h>
#include <linux/fb.h>
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
+#include <ipu_pixfmt.h>
-extern int mx51_fb_init(struct fb_videomode *mode);
+DECLARE_GLOBAL_DATA_PTR;
static struct fb_videomode nec_nl6448bc26_09c = {
"NEC_NL6448BC26-09C",
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
}
-u32 get_board_rev(void)
-{
- system_rev = get_cpu_rev();
-
- return system_rev;
-}
-
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
static void power_init_mx51(void)
{
unsigned int val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Write needed to Power Gate 2 register */
- val = pmic_reg_read(REG_POWER_MISC);
+ pmic_reg_read(p, REG_POWER_MISC, &val);
/* enable VCAM with 2.775V to enable read from PMIC */
val = VCAMCONFIG | VCAMEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
/*
* Set switchers in Auto in NORMAL mode & STANDBY mode
* Setup the switcher mode for SW1 & SW2
*/
- val = pmic_reg_read(REG_SW_4);
+ pmic_reg_read(p, REG_SW_4, &val);
val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
(SWMODE_MASK << SWMODE2_SHIFT)));
val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
- pmic_reg_write(REG_SW_4, val);
+ pmic_reg_write(p, REG_SW_4, val);
/* Setup the switcher mode for SW3 & SW4 */
- val = pmic_reg_read(REG_SW_5);
+ pmic_reg_read(p, REG_SW_5, &val);
val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
(SWMODE_MASK << SWMODE3_SHIFT));
val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
- pmic_reg_write(REG_SW_5, val);
+ pmic_reg_write(p, REG_SW_5, val);
/* Set VGEN3 to 1.8V, VCAM to 3.0V */
- val = pmic_reg_read(REG_SETTING_0);
+ pmic_reg_read(p, REG_SETTING_0, &val);
val &= ~(VCAM_MASK | VGEN3_MASK);
val |= VCAM_3_0;
- pmic_reg_write(REG_SETTING_0, val);
+ pmic_reg_write(p, REG_SETTING_0, val);
/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
- val = pmic_reg_read(REG_SETTING_1);
+ pmic_reg_read(p, REG_SETTING_1, &val);
val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
- pmic_reg_write(REG_SETTING_1, val);
+ pmic_reg_write(p, REG_SETTING_1, val);
/* Configure VGEN3 and VCAM regulators to use external PNP */
val = VGEN3CONFIG | VCAMCONFIG;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
udelay(200);
/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
VVIDEOEN | VAUDIOEN | VSDEN;
- pmic_reg_write(REG_MODE_1, val);
+ pmic_reg_write(p, REG_MODE_1, val);
- val = pmic_reg_read(REG_POWER_CTL2);
+ pmic_reg_read(p, REG_POWER_CTL2, &val);
val |= WDIRESET;
- pmic_reg_write(REG_POWER_CTL2, val);
+ pmic_reg_write(p, REG_POWER_CTL2, val);
udelay(2500);
gpio_direction_output(4, 1);
gpio_direction_output(7, 0);
- for (i = 65; i < 71; i++) {
+ for (i = 65; i < 71; i++)
gpio_direction_output(i, 0);
- }
gpio_direction_output(94, 0);
}
struct fsl_esdhc_cfg esdhc_cfg[1] = {
- {MMC_SDHC1_BASE_ADDR, 1},
+ {MMC_SDHC1_BASE_ADDR},
};
int get_mmc_getcd(u8 *cd, struct mmc *mmc)
gpio_set_value(2, 1);
mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
- ret = mx51_fb_init(&nec_nl6448bc26_09c);
+ ret = ipuv3_fb_init(&nec_nl6448bc26_09c, 0, IPU_PIX_FMT_RGB666);
if (ret)
puts("LCD cannot be configured\n");
}
udelay(2000);
#endif
- setenv("stdout", "serial");
-
return 0;
}
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int checkboard(void)
{
puts("Board: TTControl Vision II CPU V\n");