* significant 1, 2, or 3 bits of address into the chip address byte.
* This effectively makes one chip (logically) look like 2, 4, or
* 8 chips. This is handled (awkwardly) by #defining
- * CFG_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
+ * CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW and using the .1 modifier on the
* {addr} field (since .1 is the default, it doesn't actually have to
* be specified). Examples: given a memory chip at I2C chip address
* 0x50, the following would happen...
#include <common.h>
#include <command.h>
+#include <environment.h>
#include <i2c.h>
+#include <malloc.h>
#include <asm/byteorder.h>
-#if (CONFIG_COMMANDS & CFG_CMD_I2C)
-
-
/* Display values from last command.
* Memory modify remembered values are different from display memory.
*/
* When multiple buses are present, the list is an array of bus-address
* pairs. The following macros take care of this */
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
#if defined(CONFIG_I2C_MULTI_BUS)
static struct
{
uchar bus;
uchar addr;
-} i2c_no_probes[] = CFG_I2C_NOPROBES;
+} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#define GET_BUS_NUM i2c_get_bus_num()
#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b))
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a))
#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr
#else /* single bus */
-static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
#define GET_BUS_NUM 0
#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */
#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a))
#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0]))
#endif
+#if defined(CONFIG_I2C_MUX)
+static I2C_MUX_DEVICE *i2c_mux_devices = NULL;
+static int i2c_mux_busid = CONFIG_SYS_MAX_I2C_BUS;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#endif
+
static int
mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]);
-extern int cmd_get_data_size(char* arg, int default_size);
/*
* Syntax:
length = i2c_dp_last_length;
if (argc < 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
if (argv[2][j] == '.') {
alen = argv[2][j+1] - '0';
if (alen > 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
break;
return mod_i2c_mem (cmdtp, 1, flag, argc, argv);
}
-
int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
return mod_i2c_mem (cmdtp, 0, flag, argc, argv);
int j;
if ((argc < 4) || (argc > 5)) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
/*
- * Chip is always specified.
- */
+ * Chip is always specified.
+ */
chip = simple_strtoul(argv[1], NULL, 16);
/*
if (argv[2][j] == '.') {
alen = argv[2][j+1] - '0';
if (alen > 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
break;
/*
* No write delay with FRAM devices.
*/
-#if !defined(CFG_I2C_FRAM)
+#if !defined(CONFIG_SYS_I2C_FRAM)
udelay(11000);
#endif
return (0);
}
-
/* Calculate a CRC on memory
*
* Syntax:
int j;
if (argc < 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
/*
- * Chip is always specified.
- */
+ * Chip is always specified.
+ */
chip = simple_strtoul(argv[1], NULL, 16);
/*
if (argv[2][j] == '.') {
alen = argv[2][j+1] - '0';
if (alen > 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
break;
return 0;
}
-
/* Modify memory.
*
* Syntax:
extern char console_buffer[];
if (argc != 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
size = cmd_get_data_size(argv[0], 1);
/*
- * Chip is always specified.
- */
+ * Chip is always specified.
+ */
chip = simple_strtoul(argv[1], NULL, 16);
/*
if (argv[2][j] == '.') {
alen = argv[2][j+1] - '0';
if (alen > 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
break;
#endif
if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
puts ("Error writing the chip.\n");
-#ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS
- udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
if (incrflag)
addr += size;
}
} while (nbytes);
- chip = i2c_mm_last_chip;
- addr = i2c_mm_last_addr;
- alen = i2c_mm_last_alen;
+ i2c_mm_last_chip = chip;
+ i2c_mm_last_addr = addr;
+ i2c_mm_last_alen = alen;
return 0;
}
int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int j;
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
int k, skip;
uchar bus = GET_BUS_NUM;
#endif /* NOPROBES */
puts ("Valid chip addresses:");
for (j = 0; j < 128; j++) {
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
skip = 0;
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) {
}
putc ('\n');
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
puts ("Excluded chip addresses:");
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
if (COMPARE_BUS(bus,k))
return 0;
}
-
/*
* Syntax:
* iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
int j;
if (argc < 3) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
if (argv[2][j] == '.') {
alen = argv[2][j+1] - '0';
if (alen > 4) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
break;
return 0;
}
-
/*
* The SDRAM command is separately configured because many
* (most?) embedded boards don't use SDRAM DIMMs.
*/
-#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
+#if defined(CONFIG_CMD_SDRAM)
+static void print_ddr2_tcyc (u_char const b)
+{
+ printf ("%d.", (b >> 4) & 0x0F);
+ switch (b & 0x0F) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ case 0x5:
+ case 0x6:
+ case 0x7:
+ case 0x8:
+ case 0x9:
+ printf ("%d ns\n", b & 0x0F);
+ break;
+ case 0xA:
+ puts ("25 ns\n");
+ break;
+ case 0xB:
+ puts ("33 ns\n");
+ break;
+ case 0xC:
+ puts ("66 ns\n");
+ break;
+ case 0xD:
+ puts ("75 ns\n");
+ break;
+ default:
+ puts ("?? ns\n");
+ break;
+ }
+}
+
+static void decode_bits (u_char const b, char const *str[], int const do_once)
+{
+ u_char mask;
+
+ for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) {
+ if (b & mask) {
+ puts (*str);
+ if (do_once)
+ return;
+ }
+ }
+}
/*
* Syntax:
* sdram {i2c_chip}
*/
-int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
+ enum { unknown, EDO, SDRAM, DDR2 } type;
+
u_char chip;
u_char data[128];
u_char cksum;
int j;
+ static const char *decode_CAS_DDR2[] = {
+ " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD"
+ };
+
+ static const char *decode_CAS_default[] = {
+ " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1"
+ };
+
+ static const char *decode_CS_WE_default[] = {
+ " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0"
+ };
+
+ static const char *decode_byte21_default[] = {
+ " TBD (bit 7)\n",
+ " Redundant row address\n",
+ " Differential clock input\n",
+ " Registerd DQMB inputs\n",
+ " Buffered DQMB inputs\n",
+ " On-card PLL\n",
+ " Registered address/control lines\n",
+ " Buffered address/control lines\n"
+ };
+
+ static const char *decode_byte22_DDR2[] = {
+ " TBD (bit 7)\n",
+ " TBD (bit 6)\n",
+ " TBD (bit 5)\n",
+ " TBD (bit 4)\n",
+ " TBD (bit 3)\n",
+ " Supports partial array self refresh\n",
+ " Supports 50 ohm ODT\n",
+ " Supports weak driver\n"
+ };
+
+ static const char *decode_row_density_DDR2[] = {
+ "512 MiB", "256 MiB", "128 MiB", "16 GiB",
+ "8 GiB", "4 GiB", "2 GiB", "1 GiB"
+ };
+
+ static const char *decode_row_density_default[] = {
+ "512 MiB", "256 MiB", "128 MiB", "64 MiB",
+ "32 MiB", "16 MiB", "8 MiB", "4 MiB"
+ };
+
if (argc < 2) {
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
/*
* Chip is always specified.
- */
- chip = simple_strtoul(argv[1], NULL, 16);
+ */
+ chip = simple_strtoul (argv[1], NULL, 16);
- if (i2c_read(chip, 0, 1, data, sizeof(data)) != 0) {
+ if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) {
puts ("No SDRAM Serial Presence Detect found.\n");
return 1;
}
}
if (cksum != data[63]) {
printf ("WARNING: Configuration data checksum failure:\n"
- " is 0x%02x, calculated 0x%02x\n",
- data[63], cksum);
+ " is 0x%02x, calculated 0x%02x\n", data[63], cksum);
}
- printf("SPD data revision %d.%d\n",
+ printf ("SPD data revision %d.%d\n",
(data[62] >> 4) & 0x0F, data[62] & 0x0F);
- printf("Bytes used 0x%02X\n", data[0]);
- printf("Serial memory size 0x%02X\n", 1 << data[1]);
+ printf ("Bytes used 0x%02X\n", data[0]);
+ printf ("Serial memory size 0x%02X\n", 1 << data[1]);
+
puts ("Memory type ");
- switch(data[2]) {
- case 2: puts ("EDO\n"); break;
- case 4: puts ("SDRAM\n"); break;
- default: puts ("unknown\n"); break;
+ switch (data[2]) {
+ case 2:
+ type = EDO;
+ puts ("EDO\n");
+ break;
+ case 4:
+ type = SDRAM;
+ puts ("SDRAM\n");
+ break;
+ case 8:
+ type = DDR2;
+ puts ("DDR2\n");
+ break;
+ default:
+ type = unknown;
+ puts ("unknown\n");
+ break;
}
+
puts ("Row address bits ");
if ((data[3] & 0x00F0) == 0)
- printf("%d\n", data[3] & 0x0F);
+ printf ("%d\n", data[3] & 0x0F);
else
- printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
+ printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F);
+
puts ("Column address bits ");
if ((data[4] & 0x00F0) == 0)
- printf("%d\n", data[4] & 0x0F);
+ printf ("%d\n", data[4] & 0x0F);
else
- printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
- printf("Module rows %d\n", data[5]);
- printf("Module data width %d bits\n", (data[7] << 8) | data[6]);
+ printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
+
+ switch (type) {
+ case DDR2:
+ printf ("Number of ranks %d\n",
+ (data[5] & 0x07) + 1);
+ break;
+ default:
+ printf ("Module rows %d\n", data[5]);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Module data width %d bits\n", data[6]);
+ break;
+ default:
+ printf ("Module data width %d bits\n",
+ (data[7] << 8) | data[6]);
+ break;
+ }
+
puts ("Interface signal levels ");
switch(data[8]) {
- case 0: puts ("5.0v/TTL\n"); break;
+ case 0: puts ("TTL 5.0 V\n"); break;
case 1: puts ("LVTTL\n"); break;
- case 2: puts ("HSTL 1.5\n"); break;
- case 3: puts ("SSTL 3.3\n"); break;
- case 4: puts ("SSTL 2.5\n"); break;
+ case 2: puts ("HSTL 1.5 V\n"); break;
+ case 3: puts ("SSTL 3.3 V\n"); break;
+ case 4: puts ("SSTL 2.5 V\n"); break;
+ case 5: puts ("SSTL 1.8 V\n"); break;
default: puts ("unknown\n"); break;
}
- printf("SDRAM cycle time %d.%d nS\n",
- (data[9] >> 4) & 0x0F, data[9] & 0x0F);
- printf("SDRAM access time %d.%d nS\n",
- (data[10] >> 4) & 0x0F, data[10] & 0x0F);
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM cycle time ");
+ print_ddr2_tcyc (data[9]);
+ break;
+ default:
+ printf ("SDRAM cycle time %d.%d ns\n",
+ (data[9] >> 4) & 0x0F, data[9] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM access time 0.%d%d ns\n",
+ (data[10] >> 4) & 0x0F, data[10] & 0x0F);
+ break;
+ default:
+ printf ("SDRAM access time %d.%d ns\n",
+ (data[10] >> 4) & 0x0F, data[10] & 0x0F);
+ break;
+ }
+
puts ("EDC configuration ");
- switch(data[11]) {
+ switch (data[11]) {
case 0: puts ("None\n"); break;
case 1: puts ("Parity\n"); break;
case 2: puts ("ECC\n"); break;
default: puts ("unknown\n"); break;
}
+
if ((data[12] & 0x80) == 0)
puts ("No self refresh, rate ");
else
puts ("Self refresh, rate ");
+
switch(data[12] & 0x7F) {
- case 0: puts ("15.625uS\n"); break;
- case 1: puts ("3.9uS\n"); break;
- case 2: puts ("7.8uS\n"); break;
- case 3: puts ("31.3uS\n"); break;
- case 4: puts ("62.5uS\n"); break;
- case 5: puts ("125uS\n"); break;
+ case 0: puts ("15.625 us\n"); break;
+ case 1: puts ("3.9 us\n"); break;
+ case 2: puts ("7.8 us\n"); break;
+ case 3: puts ("31.3 us\n"); break;
+ case 4: puts ("62.5 us\n"); break;
+ case 5: puts ("125 us\n"); break;
default: puts ("unknown\n"); break;
}
- printf("SDRAM width (primary) %d\n", data[13] & 0x7F);
- if ((data[13] & 0x80) != 0) {
- printf(" (second bank) %d\n",
- 2 * (data[13] & 0x7F));
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM width (primary) %d\n", data[13]);
+ break;
+ default:
+ printf ("SDRAM width (primary) %d\n", data[13] & 0x7F);
+ if ((data[13] & 0x80) != 0) {
+ printf (" (second bank) %d\n",
+ 2 * (data[13] & 0x7F));
+ }
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ if (data[14] != 0)
+ printf ("EDC width %d\n", data[14]);
+ break;
+ default:
+ if (data[14] != 0) {
+ printf ("EDC width %d\n",
+ data[14] & 0x7F);
+
+ if ((data[14] & 0x80) != 0) {
+ printf (" (second bank) %d\n",
+ 2 * (data[14] & 0x7F));
+ }
+ }
+ break;
}
- if (data[14] != 0) {
- printf("EDC width %d\n",
- data[14] & 0x7F);
- if ((data[14] & 0x80) != 0)
- printf(" (second bank) %d\n",
- 2 * (data[14] & 0x7F));
+
+ if (DDR2 != type) {
+ printf ("Min clock delay, back-to-back random column addresses "
+ "%d\n", data[15]);
}
- printf("Min clock delay, back-to-back random column addresses %d\n",
- data[15]);
+
puts ("Burst length(s) ");
if (data[16] & 0x80) puts (" Page");
if (data[16] & 0x08) puts (" 8");
if (data[16] & 0x02) puts (" 2");
if (data[16] & 0x01) puts (" 1");
putc ('\n');
- printf("Number of banks %d\n", data[17]);
- puts ("CAS latency(s) ");
- if (data[18] & 0x80) puts (" TBD");
- if (data[18] & 0x40) puts (" 7");
- if (data[18] & 0x20) puts (" 6");
- if (data[18] & 0x10) puts (" 5");
- if (data[18] & 0x08) puts (" 4");
- if (data[18] & 0x04) puts (" 3");
- if (data[18] & 0x02) puts (" 2");
- if (data[18] & 0x01) puts (" 1");
- putc ('\n');
- puts ("CS latency(s) ");
- if (data[19] & 0x80) puts (" TBD");
- if (data[19] & 0x40) puts (" 6");
- if (data[19] & 0x20) puts (" 5");
- if (data[19] & 0x10) puts (" 4");
- if (data[19] & 0x08) puts (" 3");
- if (data[19] & 0x04) puts (" 2");
- if (data[19] & 0x02) puts (" 1");
- if (data[19] & 0x01) puts (" 0");
- putc ('\n');
- puts ("WE latency(s) ");
- if (data[20] & 0x80) puts (" TBD");
- if (data[20] & 0x40) puts (" 6");
- if (data[20] & 0x20) puts (" 5");
- if (data[20] & 0x10) puts (" 4");
- if (data[20] & 0x08) puts (" 3");
- if (data[20] & 0x04) puts (" 2");
- if (data[20] & 0x02) puts (" 1");
- if (data[20] & 0x01) puts (" 0");
- putc ('\n');
- puts ("Module attributes:\n");
- if (!data[21]) puts (" (none)\n");
- if (data[21] & 0x80) puts (" TBD (bit 7)\n");
- if (data[21] & 0x40) puts (" Redundant row address\n");
- if (data[21] & 0x20) puts (" Differential clock input\n");
- if (data[21] & 0x10) puts (" Registerd DQMB inputs\n");
- if (data[21] & 0x08) puts (" Buffered DQMB inputs\n");
- if (data[21] & 0x04) puts (" On-card PLL\n");
- if (data[21] & 0x02) puts (" Registered address/control lines\n");
- if (data[21] & 0x01) puts (" Buffered address/control lines\n");
- puts ("Device attributes:\n");
- if (data[22] & 0x80) puts (" TBD (bit 7)\n");
- if (data[22] & 0x40) puts (" TBD (bit 6)\n");
- if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
- else puts (" Upper Vcc tolerance 10%\n");
- if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
- else puts (" Lower Vcc tolerance 10%\n");
- if (data[22] & 0x08) puts (" Supports write1/read burst\n");
- if (data[22] & 0x04) puts (" Supports precharge all\n");
- if (data[22] & 0x02) puts (" Supports auto precharge\n");
- if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
- printf("SDRAM cycle time (2nd highest CAS latency) %d.%d nS\n",
- (data[23] >> 4) & 0x0F, data[23] & 0x0F);
- printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n",
- (data[24] >> 4) & 0x0F, data[24] & 0x0F);
- printf("SDRAM cycle time (3rd highest CAS latency) %d.%d nS\n",
- (data[25] >> 4) & 0x0F, data[25] & 0x0F);
- printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n",
- (data[26] >> 4) & 0x0F, data[26] & 0x0F);
- printf("Minimum row precharge %d nS\n", data[27]);
- printf("Row active to row active min %d nS\n", data[28]);
- printf("RAS to CAS delay min %d nS\n", data[29]);
- printf("Minimum RAS pulse width %d nS\n", data[30]);
- puts ("Density of each row ");
- if (data[31] & 0x80) puts (" 512");
- if (data[31] & 0x40) puts (" 256");
- if (data[31] & 0x20) puts (" 128");
- if (data[31] & 0x10) puts (" 64");
- if (data[31] & 0x08) puts (" 32");
- if (data[31] & 0x04) puts (" 16");
- if (data[31] & 0x02) puts (" 8");
- if (data[31] & 0x01) puts (" 4");
- puts ("MByte\n");
- printf("Command and Address setup %c%d.%d nS\n",
- (data[32] & 0x80) ? '-' : '+',
- (data[32] >> 4) & 0x07, data[32] & 0x0F);
- printf("Command and Address hold %c%d.%d nS\n",
- (data[33] & 0x80) ? '-' : '+',
- (data[33] >> 4) & 0x07, data[33] & 0x0F);
- printf("Data signal input setup %c%d.%d nS\n",
- (data[34] & 0x80) ? '-' : '+',
- (data[34] >> 4) & 0x07, data[34] & 0x0F);
- printf("Data signal input hold %c%d.%d nS\n",
- (data[35] & 0x80) ? '-' : '+',
- (data[35] >> 4) & 0x07, data[35] & 0x0F);
+ printf ("Number of banks %d\n", data[17]);
+
+ switch (type) {
+ case DDR2:
+ puts ("CAS latency(s) ");
+ decode_bits (data[18], decode_CAS_DDR2, 0);
+ putc ('\n');
+ break;
+ default:
+ puts ("CAS latency(s) ");
+ decode_bits (data[18], decode_CAS_default, 0);
+ putc ('\n');
+ break;
+ }
+
+ if (DDR2 != type) {
+ puts ("CS latency(s) ");
+ decode_bits (data[19], decode_CS_WE_default, 0);
+ putc ('\n');
+ }
+
+ if (DDR2 != type) {
+ puts ("WE latency(s) ");
+ decode_bits (data[20], decode_CS_WE_default, 0);
+ putc ('\n');
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Module attributes:\n");
+ if (data[21] & 0x80)
+ puts (" TBD (bit 7)\n");
+ if (data[21] & 0x40)
+ puts (" Analysis probe installed\n");
+ if (data[21] & 0x20)
+ puts (" TBD (bit 5)\n");
+ if (data[21] & 0x10)
+ puts (" FET switch external enable\n");
+ printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
+ if (data[20] & 0x11) {
+ printf (" %d active registers on DIMM\n",
+ (data[21] & 0x03) + 1);
+ }
+ break;
+ default:
+ puts ("Module attributes:\n");
+ if (!data[21])
+ puts (" (none)\n");
+ else
+ decode_bits (data[21], decode_byte21_default, 0);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ decode_bits (data[22], decode_byte22_DDR2, 0);
+ break;
+ default:
+ puts ("Device attributes:\n");
+ if (data[22] & 0x80) puts (" TBD (bit 7)\n");
+ if (data[22] & 0x40) puts (" TBD (bit 6)\n");
+ if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
+ else puts (" Upper Vcc tolerance 10%\n");
+ if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
+ else puts (" Lower Vcc tolerance 10%\n");
+ if (data[22] & 0x08) puts (" Supports write1/read burst\n");
+ if (data[22] & 0x04) puts (" Supports precharge all\n");
+ if (data[22] & 0x02) puts (" Supports auto precharge\n");
+ if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM cycle time (2nd highest CAS latency) ");
+ print_ddr2_tcyc (data[23]);
+ break;
+ default:
+ printf ("SDRAM cycle time (2nd highest CAS latency) %d."
+ "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM access from clock (2nd highest CAS latency) 0."
+ "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+ break;
+ default:
+ printf ("SDRAM access from clock (2nd highest CAS latency) %d."
+ "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM cycle time (3rd highest CAS latency) ");
+ print_ddr2_tcyc (data[25]);
+ break;
+ default:
+ printf ("SDRAM cycle time (3rd highest CAS latency) %d."
+ "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("SDRAM access from clock (3rd highest CAS latency) 0."
+ "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+ break;
+ default:
+ printf ("SDRAM access from clock (3rd highest CAS latency) %d."
+ "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Minimum row precharge %d.%02d ns\n",
+ (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03));
+ break;
+ default:
+ printf ("Minimum row precharge %d ns\n", data[27]);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Row active to row active min %d.%02d ns\n",
+ (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03));
+ break;
+ default:
+ printf ("Row active to row active min %d ns\n", data[28]);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("RAS to CAS delay min %d.%02d ns\n",
+ (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03));
+ break;
+ default:
+ printf ("RAS to CAS delay min %d ns\n", data[29]);
+ break;
+ }
+
+ printf ("Minimum RAS pulse width %d ns\n", data[30]);
+
+ switch (type) {
+ case DDR2:
+ puts ("Density of each row ");
+ decode_bits (data[31], decode_row_density_DDR2, 1);
+ putc ('\n');
+ break;
+ default:
+ puts ("Density of each row ");
+ decode_bits (data[31], decode_row_density_default, 1);
+ putc ('\n');
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Command and Address setup ");
+ if (data[32] >= 0xA0) {
+ printf ("1.%d%d ns\n",
+ ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
+ } else {
+ printf ("0.%d%d ns\n",
+ ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
+ }
+ break;
+ default:
+ printf ("Command and Address setup %c%d.%d ns\n",
+ (data[32] & 0x80) ? '-' : '+',
+ (data[32] >> 4) & 0x07, data[32] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ puts ("Command and Address hold ");
+ if (data[33] >= 0xA0) {
+ printf ("1.%d%d ns\n",
+ ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
+ } else {
+ printf ("0.%d%d ns\n",
+ ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
+ }
+ break;
+ default:
+ printf ("Command and Address hold %c%d.%d ns\n",
+ (data[33] & 0x80) ? '-' : '+',
+ (data[33] >> 4) & 0x07, data[33] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Data signal input setup 0.%d%d ns\n",
+ (data[34] >> 4) & 0x0F, data[34] & 0x0F);
+ break;
+ default:
+ printf ("Data signal input setup %c%d.%d ns\n",
+ (data[34] & 0x80) ? '-' : '+',
+ (data[34] >> 4) & 0x07, data[34] & 0x0F);
+ break;
+ }
+
+ switch (type) {
+ case DDR2:
+ printf ("Data signal input hold 0.%d%d ns\n",
+ (data[35] >> 4) & 0x0F, data[35] & 0x0F);
+ break;
+ default:
+ printf ("Data signal input hold %c%d.%d ns\n",
+ (data[35] & 0x80) ? '-' : '+',
+ (data[35] >> 4) & 0x07, data[35] & 0x0F);
+ break;
+ }
+
puts ("Manufacturer's JEDEC ID ");
for (j = 64; j <= 71; j++)
- printf("%02X ", data[j]);
+ printf ("%02X ", data[j]);
putc ('\n');
- printf("Manufacturing Location %02X\n", data[72]);
+ printf ("Manufacturing Location %02X\n", data[72]);
puts ("Manufacturer's Part Number ");
for (j = 73; j <= 90; j++)
- printf("%02X ", data[j]);
+ printf ("%02X ", data[j]);
putc ('\n');
- printf("Revision Code %02X %02X\n", data[91], data[92]);
- printf("Manufacturing Date %02X %02X\n", data[93], data[94]);
+ printf ("Revision Code %02X %02X\n", data[91], data[92]);
+ printf ("Manufacturing Date %02X %02X\n", data[93], data[94]);
puts ("Assembly Serial Number ");
for (j = 95; j <= 98; j++)
- printf("%02X ", data[j]);
+ printf ("%02X ", data[j]);
putc ('\n');
- printf("Speed rating PC%d\n",
- data[126] == 0x66 ? 66 : data[126]);
+ if (DDR2 != type) {
+ printf ("Speed rating PC%d\n",
+ data[126] == 0x66 ? 66 : data[126]);
+ }
return 0;
}
-#endif /* CFG_CMD_SDRAM */
+#endif
#if defined(CONFIG_I2C_CMD_TREE)
+int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ return 0;
+}
+
+#if defined(CONFIG_I2C_MUX)
+int do_i2c_add_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int ret=0;
+
+ if (argc == 1) {
+ /* show all busses */
+ I2C_MUX *mux;
+ I2C_MUX_DEVICE *device = i2c_mux_devices;
+
+ printf ("Busses reached over muxes:\n");
+ while (device != NULL) {
+ printf ("Bus ID: %x\n", device->busid);
+ printf (" reached over Mux(es):\n");
+ mux = device->mux;
+ while (mux != NULL) {
+ printf (" %s@%x ch: %x\n", mux->name, mux->chip, mux->channel);
+ mux = mux->next;
+ }
+ device = device->next;
+ }
+ } else {
+ I2C_MUX_DEVICE *dev;
+
+ dev = i2c_mux_ident_muxstring ((uchar *)argv[1]);
+ ret = 0;
+ }
+ return ret;
+}
+#endif /* CONFIG_I2C_MUX */
+
#if defined(CONFIG_I2C_MULTI_BUS)
int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
+#if defined(CONFIG_I2C_MUX)
+ if (!strncmp(argv[1], "bu", 2))
+ return do_i2c_add_bus(cmdtp, flag, --argc, ++argv);
+#endif /* CONFIG_I2C_MUX */
+ if (!strncmp(argv[1], "sp", 2))
+ return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
#if defined(CONFIG_I2C_MULTI_BUS)
if (!strncmp(argv[1], "de", 2))
return do_i2c_bus_num(cmdtp, flag, --argc, ++argv);
#endif /* CONFIG_I2C_MULTI_BUS */
- if (!strncmp(argv[1], "sp", 2))
- return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv);
if (!strncmp(argv[1], "md", 2))
return do_i2c_md(cmdtp, flag, --argc, ++argv);
if (!strncmp(argv[1], "mm", 2))
return do_i2c_crc(cmdtp, flag, --argc, ++argv);
if (!strncmp(argv[1], "pr", 2))
return do_i2c_probe(cmdtp, flag, --argc, ++argv);
+ if (!strncmp(argv[1], "re", 2))
+ return do_i2c_reset(cmdtp, flag, --argc, ++argv);
if (!strncmp(argv[1], "lo", 2))
return do_i2c_loop(cmdtp, flag, --argc, ++argv);
-#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
+#if defined(CONFIG_CMD_SDRAM)
if (!strncmp(argv[1], "sd", 2))
return do_sdram(cmdtp, flag, --argc, ++argv);
-#endif /* CFG_CMD_SDRAM */
+#endif
else
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 0;
}
#endif /* CONFIG_I2C_CMD_TREE */
/***************************************************/
+#if defined(CONFIG_I2C_CMD_TREE)
+U_BOOT_CMD(
+ i2c, 6, 1, do_i2c,
+ "I2C sub-system",
+#if defined(CONFIG_I2C_MUX)
+ "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.\n"
+#endif /* CONFIG_I2C_MUX */
+ "speed [speed] - show or set I2C bus speed\n"
+#if defined(CONFIG_I2C_MULTI_BUS)
+ "i2c dev [dev] - show or set current I2C bus\n"
+#endif /* CONFIG_I2C_MULTI_BUS */
+ "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
+ "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
+ "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
+ "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
+ "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
+ "i2c probe - show devices on the I2C bus\n"
+ "i2c reset - re-init the I2C Controller\n"
+ "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
+#if defined(CONFIG_CMD_SDRAM)
+ "i2c sdram chip - print SDRAM configuration information\n"
+#endif
+);
+#endif /* CONFIG_I2C_CMD_TREE */
U_BOOT_CMD(
imd, 4, 1, do_i2c_md, \
- "imd - i2c memory display\n", \
+ "i2c memory display", \
"chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \
);
U_BOOT_CMD(
- imm, 3, 1, do_i2c_mm,
- "imm - i2c memory modify (auto-incrementing)\n",
+ imm, 3, 1, do_i2c_mm,
+ "i2c memory modify (auto-incrementing)",
"chip address[.0, .1, .2]\n"
" - memory modify, auto increment address\n"
);
U_BOOT_CMD(
inm, 3, 1, do_i2c_nm,
- "inm - memory modify (constant address)\n",
+ "memory modify (constant address)",
"chip address[.0, .1, .2]\n - memory modify, read and keep address\n"
);
U_BOOT_CMD(
imw, 5, 1, do_i2c_mw,
- "imw - memory write (fill)\n",
+ "memory write (fill)",
"chip address[.0, .1, .2] value [count]\n - memory write (fill)\n"
);
U_BOOT_CMD(
icrc32, 5, 1, do_i2c_crc,
- "icrc32 - checksum calculation\n",
+ "checksum calculation",
"chip address[.0, .1, .2] count\n - compute CRC32 checksum\n"
);
U_BOOT_CMD(
iprobe, 1, 1, do_i2c_probe,
- "iprobe - probe to discover valid I2C chip addresses\n",
+ "probe to discover valid I2C chip addresses",
"\n -discover valid I2C chip addresses\n"
);
*/
U_BOOT_CMD(
iloop, 5, 1, do_i2c_loop,
- "iloop - infinite loop on address range\n",
+ "infinite loop on address range",
"chip address[.0, .1, .2] [# of objects]\n"
" - loop, reading a set of addresses\n"
);
-#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
+#if defined(CONFIG_CMD_SDRAM)
U_BOOT_CMD(
isdram, 2, 1, do_sdram,
- "isdram - print SDRAM configuration information\n",
+ "print SDRAM configuration information",
"chip\n - print SDRAM configuration information\n"
" (valid chip values 50..57)\n"
);
#endif
-#if defined(CONFIG_I2C_CMD_TREE)
-U_BOOT_CMD(
- i2c, 6, 1, do_i2c,
- "i2c - I2C sub-system\n",
-#if defined(CONFIG_I2C_MULTI_BUS)
- "dev [dev] - show or set current I2C bus\n"
-#endif /* CONFIG_I2C_MULTI_BUS */
- "i2c speed [speed] - show or set I2C bus speed\n"
- "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n"
- "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
- "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
- "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
- "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
- "i2c probe - show devices on the I2C bus\n"
- "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n"
-#if (CONFIG_COMMANDS & CFG_CMD_SDRAM)
- "i2c sdram chip - print SDRAM configuration information\n"
-#endif /* CFG_CMD_SDRAM */
-);
-#endif /* CONFIG_I2C_CMD_TREE */
+#if defined(CONFIG_I2C_MUX)
+
+int i2c_mux_add_device(I2C_MUX_DEVICE *dev)
+{
+ I2C_MUX_DEVICE *devtmp = i2c_mux_devices;
+
+ if (i2c_mux_devices == NULL) {
+ i2c_mux_devices = dev;
+ return 0;
+ }
+ while (devtmp->next != NULL)
+ devtmp = devtmp->next;
+
+ devtmp->next = dev;
+ return 0;
+}
+
+I2C_MUX_DEVICE *i2c_mux_search_device(int id)
+{
+ I2C_MUX_DEVICE *device = i2c_mux_devices;
+
+ while (device != NULL) {
+ if (device->busid == id)
+ return device;
+ device = device->next;
+ }
+ return NULL;
+}
+
+/* searches in the buf from *pos the next ':'.
+ * returns:
+ * 0 if found (with *pos = where)
+ * < 0 if an error occured
+ * > 0 if the end of buf is reached
+ */
+static int i2c_mux_search_next (int *pos, uchar *buf, int len)
+{
+ while ((buf[*pos] != ':') && (*pos < len)) {
+ *pos += 1;
+ }
+ if (*pos >= len)
+ return 1;
+ if (buf[*pos] != ':')
+ return -1;
+ return 0;
+}
+
+static int i2c_mux_get_busid (void)
+{
+ int tmp = i2c_mux_busid;
+
+ i2c_mux_busid ++;
+ return tmp;
+}
+
+/* Analyses a Muxstring and sends immediately the
+ Commands to the Muxes. Runs from Flash.
+ */
+int i2c_mux_ident_muxstring_f (uchar *buf)
+{
+ int pos = 0;
+ int oldpos;
+ int ret = 0;
+ int len = strlen((char *)buf);
+ int chip;
+ uchar channel;
+ int was = 0;
+
+ while (ret == 0) {
+ oldpos = pos;
+ /* search name */
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret != 0)
+ printf ("ERROR\n");
+ /* search address */
+ pos ++;
+ oldpos = pos;
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret != 0)
+ printf ("ERROR\n");
+ buf[pos] = 0;
+ chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
+ buf[pos] = ':';
+ /* search channel */
+ pos ++;
+ oldpos = pos;
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret < 0)
+ printf ("ERROR\n");
+ was = 0;
+ if (buf[pos] != 0) {
+ buf[pos] = 0;
+ was = 1;
+ }
+ channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
+ if (was)
+ buf[pos] = ':';
+ if (i2c_write(chip, 0, 0, &channel, 1) != 0) {
+ printf ("Error setting Mux: chip:%x channel: \
+ %x\n", chip, channel);
+ return -1;
+ }
+ pos ++;
+ oldpos = pos;
-#endif /* CFG_CMD_I2C */
+ }
+
+ return 0;
+}
+
+/* Analyses a Muxstring and if this String is correct
+ * adds a new I2C Bus.
+ */
+I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf)
+{
+ I2C_MUX_DEVICE *device;
+ I2C_MUX *mux;
+ int pos = 0;
+ int oldpos;
+ int ret = 0;
+ int len = strlen((char *)buf);
+ int was = 0;
+
+ device = (I2C_MUX_DEVICE *)malloc (sizeof(I2C_MUX_DEVICE));
+ device->mux = NULL;
+ device->busid = i2c_mux_get_busid ();
+ device->next = NULL;
+ while (ret == 0) {
+ mux = (I2C_MUX *)malloc (sizeof(I2C_MUX));
+ mux->next = NULL;
+ /* search name of mux */
+ oldpos = pos;
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret != 0)
+ printf ("%s no name.\n", __FUNCTION__);
+ mux->name = (char *)malloc (pos - oldpos + 1);
+ memcpy (mux->name, &buf[oldpos], pos - oldpos);
+ mux->name[pos - oldpos] = 0;
+ /* search address */
+ pos ++;
+ oldpos = pos;
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret != 0)
+ printf ("%s no mux address.\n", __FUNCTION__);
+ buf[pos] = 0;
+ mux->chip = simple_strtoul((char *)&buf[oldpos], NULL, 16);
+ buf[pos] = ':';
+ /* search channel */
+ pos ++;
+ oldpos = pos;
+ ret = i2c_mux_search_next(&pos, buf, len);
+ if (ret < 0)
+ printf ("%s no mux channel.\n", __FUNCTION__);
+ was = 0;
+ if (buf[pos] != 0) {
+ buf[pos] = 0;
+ was = 1;
+ }
+ mux->channel = simple_strtoul((char *)&buf[oldpos], NULL, 16);
+ if (was)
+ buf[pos] = ':';
+ if (device->mux == NULL)
+ device->mux = mux;
+ else {
+ I2C_MUX *muxtmp = device->mux;
+ while (muxtmp->next != NULL) {
+ muxtmp = muxtmp->next;
+ }
+ muxtmp->next = mux;
+ }
+ pos ++;
+ oldpos = pos;
+ }
+ if (ret > 0) {
+ /* Add Device */
+ i2c_mux_add_device (device);
+ return device;
+ }
+
+ return NULL;
+}
+
+int i2x_mux_select_mux(int bus)
+{
+ I2C_MUX_DEVICE *dev;
+ I2C_MUX *mux;
+
+ if ((gd->flags & GD_FLG_RELOC) != GD_FLG_RELOC) {
+ /* select Default Mux Bus */
+#if defined(CONFIG_SYS_I2C_IVM_BUS)
+ i2c_mux_ident_muxstring_f ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
+#else
+ {
+ unsigned char *buf;
+ buf = (unsigned char *) getenv("EEprom_ivm");
+ if (buf != NULL)
+ i2c_mux_ident_muxstring_f (buf);
+ }
+#endif
+ return 0;
+ }
+ dev = i2c_mux_search_device(bus);
+ if (dev == NULL)
+ return -1;
+
+ mux = dev->mux;
+ while (mux != NULL) {
+ if (i2c_write(mux->chip, 0, 0, &mux->channel, 1) != 0) {
+ printf ("Error setting Mux: chip:%x channel: \
+ %x\n", mux->chip, mux->channel);
+ return -1;
+ }
+ mux = mux->next;
+ }
+ return 0;
+}
+#endif /* CONFIG_I2C_MUX */
projects / karo-tx-uboot.git / blobdiff