Big white-space cleanup.

[karo-tx-uboot.git] / cpu / mpc83xx / spd_sdram.c

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index c9151d7120705a61b63c3f40990f0aca7c5651b1..76f2474491a7b36441d5608e8bff64b95f62996b 100644 (file)
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -34,10 +34,13 @@
 #include <asm/mmu.h>
 #include <spd_sdram.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void board_add_ram_info(int use_default)
 {
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile ddr83xx_t *ddr = &immap->ddr;
+       char buf[32];
 
        printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
                           >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
@@ -48,9 +51,11 @@ void board_add_ram_info(int use_default)
                puts(", 64-bit");
 
        if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
-               puts(", ECC on)");
+               puts(", ECC on");
        else
-               puts(", ECC off)");
+               puts(", ECC off");
+
+       printf(", %s MHz)", strmhz(buf, gd->mem_clk));
 
 #if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
        puts("\nSDRAM: ");
@@ -60,8 +65,6 @@ void board_add_ram_info(int use_default)
 
 #ifdef CONFIG_SPD_EEPROM
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void dma_init(void);
 extern uint dma_check(void);
@@ -507,7 +510,7 @@ long int spd_sdram()
        ddr->timing_cfg_1 =
            (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |    /* PRETOACT */
             ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
-            (trcd_clk << 20 ) |                                /* ACTTORW */
+            (trcd_clk << 20 ) |                                /* ACTTORW */
             (caslat_ctrl << 16 ) |                             /* CASLAT */
             (trfc_low << 12 ) |                                /* REFEC */
             ((twr_clk & 0x07) << 8) |                          /* WRRREC */
@@ -598,7 +601,7 @@ long int spd_sdram()
        debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
 
        /* Check DIMM data bus width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
                else
@@ -760,7 +763,7 @@ long int spd_sdram()
                sdram_cfg |= SDRAM_CFG_RD_EN;
 
        /* The DIMM is 32bit width */
-       if (spd.dataw_lsb == 0x20) {
+       if (spd.dataw_lsb < 64) {
                if (spd.mem_type == SPD_MEMTYPE_DDR)
                        sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
                if (spd.mem_type == SPD_MEMTYPE_DDR2)