kgdb: drop duplicate debugger_exception_handler

[karo-tx-uboot.git] / cpu / ppc4xx / traps.c

diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index f5365cb76a66937c1e3f7ac808d8aae890132d5f..cb35faf081414d30526c74b3458ba0c93abda684 100644 (file)
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -38,10 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_CMD_KGDB)
-int (*debugger_exception_handler)(struct pt_regs *) = 0;
-#endif
-
 /* Returns 0 if exception not found and fixup otherwise.  */
 extern unsigned long search_exception_table(unsigned long);
 
@@ -151,12 +147,6 @@ MachineCheckException(struct pt_regs *regs)
        int uncorr_ecc = 0;
 #endif
 
-       /* Probing PCI(E) using config cycles may cause this exception
-        * when a device is not present. To gracefully recover in such
-        * scenarios config read/write routines need to be instrumented in
-        * order to return via fixup handler. For examples refer to
-        * pcie_in_8(), pcie_in_le16() and pcie_in_le32()
-        */
        if ((fixup = search_exception_table(regs->nip)) != 0) {
                regs->nip = fixup;
                val = mfspr(MCSR);
@@ -176,7 +166,7 @@ MachineCheckException(struct pt_regs *regs)
 
        val = get_esr();
 
-#if !defined(CONFIG_440)
+#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
        if (val& ESR_IMCP) {
                printf("Instruction");
                mtspr(ESR, val & ~ESR_IMCP);
@@ -185,7 +175,7 @@ MachineCheckException(struct pt_regs *regs)
        }
        printf(" machine check.\n");
 
-#elif defined(CONFIG_440)
+#elif defined(CONFIG_440) || defined(CONFIG_405EX)
        if (val& ESR_IMCP){
                printf("Instruction Synchronous Machine Check exception\n");
                mtspr(SPRN_ESR, val & ~ESR_IMCP);
@@ -193,10 +183,15 @@ MachineCheckException(struct pt_regs *regs)
                val = mfspr(MCSR);
                if (val & MCSR_IB)
                        printf("Instruction Read PLB Error\n");
+#if defined(CONFIG_440)
                if (val & MCSR_DRB)
                        printf("Data Read PLB Error\n");
                if (val & MCSR_DWB)
                        printf("Data Write PLB Error\n");
+#else
+               if (val & MCSR_DB)
+                       printf("Data PLB Error\n");
+#endif
                if (val & MCSR_TLBP)
                        printf("TLB Parity Error\n");
                if (val & MCSR_ICP){
@@ -215,7 +210,7 @@ MachineCheckException(struct pt_regs *regs)
        }
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        mfsdram(DDR0_00, val) ;
-       printf("DDR0: DDR0_00 %p\n", val);
+       printf("DDR0: DDR0_00 %lx\n", val);
        val = (val >> 16) & 0xff;
        if (val & 0x80)
                printf("DDR0: At least one interrupt active\n");
@@ -264,44 +259,44 @@ MachineCheckException(struct pt_regs *regs)
                break;
        default:
                mfsdram(DDR0_01, value2);
-               printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
+               printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
        }
        mfsdram(DDR0_23, val);
        if (((val >> 16) & 0xff) && corr_ecc)
-               printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
+               printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
                       (val >> 16) & 0xff);
        mfsdram(DDR0_23, val);
        if (((val >> 8) & 0xff) && uncorr_ecc)
-               printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
+               printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
                       (val >> 8) & 0xff);
        mfsdram(DDR0_33, val);
        if (val)
                printf("DDR0: Address of command that caused an "
-                      "Out-of-Range interrupt %p\n", val);
+                      "Out-of-Range interrupt %lx\n", val);
        mfsdram(DDR0_34, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+               printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
        mfsdram(DDR0_35, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Address of uncorrectable ECC event %p\n", val);
+               printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
        mfsdram(DDR0_36, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_37, val);
        if (val && uncorr_ecc)
-               printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_38, val);
        if (val && corr_ecc)
-               printf("DDR0: Address of correctable ECC event %p\n", val);
+               printf("DDR0: Address of correctable ECC event %lx\n", val);
        mfsdram(DDR0_39, val);
        if (val && corr_ecc)
-               printf("DDR0: Address of correctable ECC event %p\n", val);
+               printf("DDR0: Address of correctable ECC event %lx\n", val);
        mfsdram(DDR0_40, val);
        if (val && corr_ecc)
-               printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
        mfsdram(DDR0_41, val);
        if (val && corr_ecc)
-               printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
+               printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
 #endif /* CONFIG_440EPX */
 #endif /* CONFIG_440 */
        show_regs(regs);