Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / drivers / fpga / virtex2.c

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b26d231511e78ff2d58b0042878f69a203ea12f4..b5a895d41a7343c783bf8bfda2d300f8e06d6dac 100644 (file)
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -3,24 +3,7 @@
  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  * Keith Outwater, keith_outwater@mvis.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -221,7 +204,7 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                 * There is no maximum value for the pulse width.  Check to make
                 * sure that INIT_B goes low after assertion of PROG_B
                 */
-               (*fn->pgm) (TRUE, TRUE, cookie);
+               (*fn->pgm) (true, true, cookie);
                udelay (10);
                ts = get_timer (0);
                do {
@@ -234,9 +217,9 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                        }
                } while (!(*fn->init) (cookie));
 
-               (*fn->pgm) (FALSE, TRUE, cookie);
+               (*fn->pgm) (false, true, cookie);
                CONFIG_FPGA_DELAY ();
-               (*fn->clk) (TRUE, TRUE, cookie);
+               (*fn->clk) (true, true, cookie);
 
                /*
                 * Start a timer and wait for INIT_B to go high
@@ -253,8 +236,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                        }
                } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
 
-               (*fn->wr) (TRUE, TRUE, cookie);
-               (*fn->cs) (TRUE, TRUE, cookie);
+               (*fn->wr) (true, true, cookie);
+               (*fn->cs) (true, true, cookie);
 
                udelay (10000);
 
@@ -286,15 +269,15 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                        }
 #endif
 
-                       (*fn->wdata) (data[bytecount++], TRUE, cookie);
+                       (*fn->wdata) (data[bytecount++], true, cookie);
                        CONFIG_FPGA_DELAY ();
 
                        /*
                         * Cycle the clock pin
                         */
-                       (*fn->clk) (FALSE, TRUE, cookie);
+                       (*fn->clk) (false, true, cookie);
                        CONFIG_FPGA_DELAY ();
-                       (*fn->clk) (TRUE, TRUE, cookie);
+                       (*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
                        ts = get_timer (0);
@@ -319,8 +302,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
                 */
                CONFIG_FPGA_DELAY ();
-               (*fn->cs) (FALSE, TRUE, cookie);
-               (*fn->wr) (FALSE, TRUE, cookie);
+               (*fn->cs) (false, true, cookie);
+               (*fn->wr) (false, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
                putc ('\n');
@@ -381,8 +364,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
                printf ("Starting Dump of FPGA Device %d...\n", cookie);
 
-               (*fn->cs) (TRUE, TRUE, cookie);
-               (*fn->clk) (TRUE, TRUE, cookie);
+               (*fn->cs) (true, true, cookie);
+               (*fn->clk) (true, true, cookie);
 
                while (bytecount < bsize) {
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -394,8 +377,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
                        /*
                         * Cycle the clock and read the data
                         */
-                       (*fn->clk) (FALSE, TRUE, cookie);
-                       (*fn->clk) (TRUE, TRUE, cookie);
+                       (*fn->clk) (false, true, cookie);
+                       (*fn->clk) (true, true, cookie);
                        (*fn->rdata) (&(data[bytecount++]), cookie);
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
                        if (bytecount % (bsize / 40) == 0)
@@ -406,9 +389,9 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
                /*
                 * Deassert CS_B and cycle the clock to deselect the device.
                 */
-               (*fn->cs) (FALSE, FALSE, cookie);
-               (*fn->clk) (FALSE, TRUE, cookie);
-               (*fn->clk) (TRUE, TRUE, cookie);
+               (*fn->cs) (false, false, cookie);
+               (*fn->clk) (false, true, cookie);
+               (*fn->clk) (true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
                putc ('\n');