Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / drivers / fpga / zynqpl.c

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 8cc16fd2c2db3da9c77dabbd1e2ad89cd9bb36eb..15900c9ef262eb0f498a59b4a598672f67430958 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -4,12 +4,13 @@
  * (C) Copyright 2012
  * Joe Hershberger <joe.hershberger@ni.com>
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
 #include <zynqpl.h>
+#include <asm/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
@@ -23,6 +24,7 @@
 #define DEVCFG_STATUS_DMA_CMD_Q_E      0x40000000
 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK        0x30000000
 #define DEVCFG_STATUS_PCFG_INIT                0x00000010
+#define DEVCFG_MCTRL_PCAP_LPBK         0x00000010
 #define DEVCFG_MCTRL_RFIFO_FLUSH       0x00000002
 #define DEVCFG_MCTRL_WFIFO_FLUSH       0x00000001
 
@@ -31,7 +33,7 @@
 #endif
 
 #ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ        /* 1 s */
+#define CONFIG_SYS_FPGA_PROG_TIME      (CONFIG_SYS_HZ * 4) /* 4 s */
 #endif
 
 int zynq_info(Xilinx_desc *desc)
@@ -176,8 +178,24 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                return FPGA_FAIL;
        }
 
-       if ((u32)buf_start & 0x3) {
-               u32 *new_buf = (u32 *)((u32)buf & ~0x3);
+       if ((u32)buf < SZ_1M) {
+               printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+                      __func__, (u32)buf);
+               return FPGA_FAIL;
+       }
+
+       if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+               u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+
+               /*
+                * This might be dangerous but permits to flash if
+                * ARCH_DMA_MINALIGN is greater than header size
+                */
+               if (new_buf > buf_start) {
+                       debug("%s: Aligned buffer is after buffer start\n",
+                             __func__);
+                       new_buf -= ARCH_DMA_MINALIGN;
+               }
 
                printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
                       (u32)buf_start, (u32)new_buf, swap);
@@ -200,6 +218,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
                swap = SWAP_DONE;
        }
 
+       /* Clear loopback bit */
+       clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
+
        if (!partialbit) {
                zynq_slcr_devcfg_disable();
 
@@ -280,6 +301,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
        debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
        debug("%s: Size = %zu\n", __func__, bsize);
 
+       /* flush(clean & invalidate) d-cache range buf */
+       flush_dcache_range((u32)buf, (u32)buf +
+                          roundup(bsize, ARCH_DMA_MINALIGN));
+
        /* Set up the transfer */
        writel((u32)buf | 1, &devcfg_base->dma_src_addr);
        writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);