Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / drivers / mmc / exynos_dw_mmc.c

diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 4ef9fec0e4d1ce90214b8504dff59111ebec4138..de8cdcc42b3db83f631b358f24e90cc1d2c5dbed 100644 (file)
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -29,9 +29,35 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
        dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val);
 }
 
-unsigned int exynos_dwmci_get_clk(int dev_index)
+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
 {
-       return get_mmc_clk(dev_index);
+       unsigned long sclk;
+       int8_t clk_div;
+
+       /*
+        * Since SDCLKIN is divided inside controller by the DIVRATIO
+        * value set in the CLKSEL register, we need to use the same output
+        * clock value to calculate the CLKDIV value.
+        * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
+        */
+       clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
+                       & DWMCI_DIVRATIO_MASK) + 1;
+       sclk = get_mmc_clk(host->dev_index);
+
+       return sclk / clk_div;
+}
+
+static void exynos_dwmci_board_init(struct dwmci_host *host)
+{
+       if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
+               dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
+               dwmci_writel(host, EMMCP_SEND0, 0);
+               dwmci_writel(host, EMMCP_CTRL0,
+                            MPSCTRL_SECURE_READ_BIT |
+                            MPSCTRL_SECURE_WRITE_BIT |
+                            MPSCTRL_NON_SECURE_READ_BIT |
+                            MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
+       }
 }
 
 /*
@@ -62,6 +88,10 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
        host->name = "EXYNOS DWMMC";
        host->ioaddr = (void *)regbase;
        host->buswidth = bus_width;
+#ifdef CONFIG_EXYNOS5420
+       host->quirks = DWMCI_QUIRK_DISABLE_SMU;
+#endif
+       host->board_init = exynos_dwmci_board_init;
 
        if (clksel) {
                host->clksel_val = clksel;
@@ -74,7 +104,7 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
 
        host->clksel = exynos_dwmci_clksel;
        host->dev_index = index;
-       host->mmc_clk = exynos_dwmci_get_clk;
+       host->get_mmc_clk = exynos_dwmci_get_clk;
        /* Add the mmc channel to be registered with mmc core */
        if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
                debug("dwmmc%d registration failed\n", index);