Merge branch 'master' of git://git.denx.de/u-boot-x86

[karo-tx-uboot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a2f35e3e99159dc0481737a0bb4d1f1e55fc0da6..b90f3e77698636a1fff74d01e930fa4d355e7468 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -68,7 +68,7 @@ struct fsl_esdhc {
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
-uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 {
        uint xfertyp = 0;
 
@@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
        } else {
+               flush_dcache_range((ulong)data->src,
+                                  (ulong)data->src+data->blocks
+                                        *data->blocksize);
+
                if (wml_value > WML_WR_WML_MAX)
                        wml_value = WML_WR_WML_MAX_VAL;
                if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
@@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        return 0;
 }
 
-
+static void check_and_invalidate_dcache_range
+       (struct mmc_cmd *cmd,
+        struct mmc_data *data) {
+       unsigned start = (unsigned)data->dest ;
+       unsigned size = roundup(ARCH_DMA_MINALIGN,
+                               data->blocks*data->blocksize);
+       unsigned end = start+size ;
+       invalidate_dcache_range(start, end);
+}
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
  * a command pointer, and an optional data pointer.
@@ -307,19 +319,59 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 #else
        esdhc_write32(&regs->xfertyp, xfertyp);
 #endif
+
+       /* Mask all irqs */
+       esdhc_write32(&regs->irqsigen, 0);
+
        /* Wait for the command to complete */
-       while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
+       while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
                ;
 
+       if (data && (data->flags & MMC_DATA_READ))
+               check_and_invalidate_dcache_range(cmd, data);
+
        irqstat = esdhc_read32(&regs->irqstat);
        esdhc_write32(&regs->irqstat, irqstat);
 
+       /* Reset CMD and DATA portions on error */
+       if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
+               esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
+                             SYSCTL_RSTC);
+               while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
+                       ;
+
+               if (data) {
+                       esdhc_write32(&regs->sysctl,
+                                     esdhc_read32(&regs->sysctl) |
+                                     SYSCTL_RSTD);
+                       while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
+                               ;
+               }
+       }
+
        if (irqstat & CMD_ERR)
                return COMM_ERR;
 
        if (irqstat & IRQSTAT_CTOE)
                return TIMEOUT;
 
+       /* Workaround for ESDHC errata ENGcm03648 */
+       if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
+               int timeout = 2500;
+
+               /* Poll on DATA0 line for cmd with busy signal for 250 ms */
+               while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
+                                       PRSSTAT_DAT0)) {
+                       udelay(100);
+                       timeout--;
+               }
+
+               if (timeout <= 0) {
+                       printf("Timeout waiting for DAT0 to go high!\n");
+                       return TIMEOUT;
+               }
+       }
+
        /* Copy the response to the response buffer */
        if (cmd->resp_type & MMC_RSP_136) {
                u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
@@ -358,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-       int sdhc_clk = gd->sdhc_clk;
        int div, pre_div;
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
        volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+       int sdhc_clk = cfg->sdhc_clk;
        uint clk;
 
        if (clock < mmc->f_min)
@@ -427,9 +479,10 @@ static int esdhc_init(struct mmc *mmc)
        while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
                udelay(1000);
 
+#ifndef ARCH_MXC
        /* Enable cache snooping */
-       if (cfg && !cfg->no_snoop)
-               esdhc_write32(&regs->scr, 0x00000040);
+       esdhc_write32(&regs->scr, 0x00000040);
+#endif
 
        esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
@@ -491,6 +544,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        /* First reset the eSDHC controller */
        esdhc_reset(regs);
 
+       esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+                               | SYSCTL_IPGEN | SYSCTL_CKEN);
+
        mmc->priv = cfg;
        mmc->send_cmd = esdhc_send_cmd;
        mmc->set_ios = esdhc_set_ios;
@@ -521,13 +577,13 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
                return -1;
        }
 
-       mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+       mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 
        if (caps & ESDHC_HOSTCAPBLT_HSS)
                mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
        mmc->f_min = 400000;
-       mmc->f_max = MIN(gd->sdhc_clk, 52000000);
+       mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
 
        mmc->b_max = 0;
        mmc_register(mmc);
@@ -542,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
        cfg = malloc(sizeof(struct fsl_esdhc_cfg));
        memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
        cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+       cfg->sdhc_clk = gd->arch.sdhc_clk;
        return fsl_esdhc_initialize(bis, cfg);
 }
 
@@ -559,7 +616,7 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
 #endif
 
        do_fixup_by_compat_u32(blob, compat, "clock-frequency",
-                              gd->sdhc_clk, 1);
+                              gd->arch.sdhc_clk, 1);
 
        do_fixup_by_compat(blob, compat, "status", "okay",
                           4 + 1, 1);