nand, atmel: remove udelay in spl_nand_erase_one()

[karo-tx-uboot.git] / drivers / mtd / nand / atmel_nand.c

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 620b6e8ff9a4cfac6745eb6477718ce14a93d05f..0d4f327ed71e2196b01e88eeaab1486f7ae0229f 100644 (file)
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -44,6 +44,7 @@ struct atmel_nand_host {
        u8              pmecc_corr_cap;
        u16             pmecc_sector_size;
        u32             pmecc_index_table_offset;
+       u32             pmecc_version;
 
        int             pmecc_bytes_per_sector;
        int             pmecc_sector_number;
@@ -486,6 +487,10 @@ static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
        int i, err_nbr, eccbytes;
        uint8_t *buf_pos;
 
+       /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
+       if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
+               goto normal_check;
+
        eccbytes = nand_chip->ecc.bytes;
        for (i = 0; i < eccbytes; i++)
                if (ecc[i] != 0xff)
@@ -961,6 +966,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
        nand->ecc.write_page = atmel_nand_pmecc_write_page;
        nand->ecc.strength = cap;
 
+       /* Check the PMECC ip version */
+       host->pmecc_version = pmecc_readl(host->pmerrloc, version);
+       dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
+
        atmel_pmecc_core_init(mtd);
 
        return 0;
@@ -1369,9 +1378,7 @@ int spl_nand_erase_one(int block, int page)
        hwctrl(&mtd, (page_addr >> 16) & 0x0f,
               NAND_CTRL_ALE | NAND_CTRL_CHANGE);
 #endif
-
        hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-       udelay(2000);
 
        while (!this->dev_ready(&mtd))
                ;
@@ -1447,6 +1454,9 @@ int board_nand_init(struct nand_chip *nand)
        nand->dev_ready = at91_nand_wait_ready;
 #endif
        nand->chip_delay = 20;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+       nand->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
 
 #ifdef CONFIG_ATMEL_NAND_HWECC
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
@@ -1513,6 +1523,9 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
        nand->dev_ready = at91_nand_ready;
 #endif
        nand->chip_delay = 75;
+#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
+       nand->bbt_options |= NAND_BBT_USE_FLASH;
+#endif
 
        ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
        if (ret)