sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END

[karo-tx-uboot.git] / drivers / mtd / nand / fsl_elbc_spl.c

diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c
index 7e5599ac634b4dd784efc38da4be4da3976418c3..29521359a50da56e1017e2580ab6e6e33b1bfd9d 100644 (file)
--- a/drivers/mtd/nand/fsl_elbc_spl.c
+++ b/drivers/mtd/nand/fsl_elbc_spl.c
@@ -34,7 +34,11 @@ static void nand_wait(void)
        }
 }
 
+#ifdef CONFIG_TPL_BUILD
+int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#else
 static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+#endif
 {
        fsl_lbc_t *regs = LBC_BASE_ADDR;
        uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
@@ -55,20 +59,20 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
        if (large) {
                fmr |= FMR_ECCM;
                out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
-                                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
+                                    (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
                out_be32(&regs->fir,
-                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
-                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
-                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
-                        (FIR_OP_CW1 << FIR_OP3_SHIFT) |
-                        (FIR_OP_RBW << FIR_OP4_SHIFT));
+                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
+                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
+                        (FIR_OP_CW1 << FIR_OP3_SHIFT) |
+                        (FIR_OP_RBW << FIR_OP4_SHIFT));
        } else {
                out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
                out_be32(&regs->fir,
-                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
-                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
-                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
-                        (FIR_OP_RBW << FIR_OP3_SHIFT));
+                        (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+                        (FIR_OP_CA  << FIR_OP1_SHIFT) |
+                        (FIR_OP_PA  << FIR_OP2_SHIFT) |
+                        (FIR_OP_RBW << FIR_OP3_SHIFT));
        }
 
        out_be32(&regs->fbcr, 0);
@@ -113,6 +117,15 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
        return 0;
 }
 
+/*
+ * Defines a static function nand_load_image() here, because non-static makes
+ * the code too large for certain SPLs(minimal SPL, maximum size <= 4Kbytes)
+ */
+#ifndef CONFIG_TPL_BUILD
+#define nand_spl_load_image(offs, uboot_size, vdst) \
+       nand_load_image(offs, uboot_size, vdst)
+#endif
+
 /*
  * The main entry for NAND booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -124,17 +137,17 @@ void nand_boot(void)
        /*
         * Load U-Boot image from NAND into RAM
         */
-       nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
-                       CONFIG_SYS_NAND_U_BOOT_SIZE,
-                       (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+       nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+                           CONFIG_SYS_NAND_U_BOOT_SIZE,
+                           (void *)CONFIG_SYS_NAND_U_BOOT_DST);
 
 #ifdef CONFIG_NAND_ENV_DST
-       nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-                       (void *)CONFIG_NAND_ENV_DST);
+       nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+                           (void *)CONFIG_NAND_ENV_DST);
 
 #ifdef CONFIG_ENV_OFFSET_REDUND
-       nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
-                       (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+       nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+                           (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
 #endif
 #endif