#include <linux/mii.h>
#include <asm/blackfin.h>
+#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
#define TOUT_LOOP 1000000
-ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
-ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
+static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
+static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx; /* index of the current RX buffer */
static u16 rxIdx; /* index of the current TX buffer */
/* DMAx_CONFIG values at DMA Restart */
-const ADI_DMA_CONFIG_REG rxdmacfg = {
- .b_DMA_EN = 1, /* enabled */
- .b_WNR = 1, /* write to memory */
- .b_WDSIZE = 2, /* wordsize is 32 bits */
- .b_DMA2D = 0,
- .b_RESTART = 0,
- .b_DI_SEL = 0,
- .b_DI_EN = 0, /* no interrupt */
- .b_NDSIZE = 5, /* 5 half words is desc size */
- .b_FLOW = 7 /* large desc flow */
-};
-
-const ADI_DMA_CONFIG_REG txdmacfg = {
- .b_DMA_EN = 1, /* enabled */
- .b_WNR = 0, /* read from memory */
- .b_WDSIZE = 2, /* wordsize is 32 bits */
- .b_DMA2D = 0,
- .b_RESTART = 0,
- .b_DI_SEL = 0,
- .b_DI_EN = 0, /* no interrupt */
- .b_NDSIZE = 5, /* 5 half words is desc size */
- .b_FLOW = 7 /* large desc flow */
+static const union {
+ u16 data;
+ ADI_DMA_CONFIG_REG reg;
+} txdmacfg = {
+ .reg = {
+ .b_DMA_EN = 1, /* enabled */
+ .b_WNR = 0, /* read from memory */
+ .b_WDSIZE = 2, /* wordsize is 32 bits */
+ .b_DMA2D = 0,
+ .b_RESTART = 0,
+ .b_DI_SEL = 0,
+ .b_DI_EN = 0, /* no interrupt */
+ .b_NDSIZE = 5, /* 5 half words is desc size */
+ .b_FLOW = 7 /* large desc flow */
+ },
};
static int bfin_miiphy_wait(void)
return 0;
}
-static int bfin_miiphy_read(char *devname, uchar addr, uchar reg, ushort *val)
+static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
{
if (bfin_miiphy_wait())
return 1;
return 0;
}
-static int bfin_miiphy_write(char *devname, uchar addr, uchar reg, ushort val)
+static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
{
if (bfin_miiphy_wait())
return 1;
hang();
memset(dev, 0, sizeof(*dev));
- sprintf(dev->name, "Blackfin EMAC");
+ strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
+ dev->write_hwaddr = bfin_EMAC_setup_addr;
eth_register(dev);
return 0;
}
-static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
- int length)
+static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
{
int i;
int result = 0;
goto out;
}
- if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) {
+ if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
printf("Ethernet: tx DMA error\n");
goto out;
}
- for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) {
+ for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
- *pDMA2_NEXT_DESC_PTR = &txbuf[txIdx]->Dma[0];
- *pDMA2_CONFIG = *(u16 *) (void *)(&txdmacfg);
- *pEMAC_OPMODE |= TE;
+ bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
+ bfin_write_DMA2_CONFIG(txdmacfg.data);
+ bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
printf("Ethernet: bad frame\n");
break;
}
+
+ debug("%s: len = %d\n", __func__, length - 4);
+
NetRxPackets[rxIdx] =
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
NetReceive(NetRxPackets[rxIdx], length - 4);
- *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR;
+ bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
+#ifndef CONFIG_BFIN_MAC_PINS
+# ifdef CONFIG_RMII
+# define CONFIG_BFIN_MAC_PINS P_RMII0
+# else
+# define CONFIG_BFIN_MAC_PINS P_MII0
+# endif
+#endif
+
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
+ const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
u16 phydat;
size_t count;
/* Enable PHY output */
- *pVR_CTL |= CLKBUFOE;
+ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
/* Set all the pins to peripheral mode */
-#ifdef CONFIG_RMII
- /* grab RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
- PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
- *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
-# else
- *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
-# endif
-#else
- /* grab MII & RMII pins */
-# if defined(__ADSPBF51x__)
- *pPORTF_MUX = (*pPORTF_MUX & \
- ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
- PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
- *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
- *pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
- *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
- *pPORTG_FER |= PG14 | PG15;
- *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
- *pPORTH_FER = -1; /* all pins */
-# else
- *pPORTH_FER = -1; /* all pins */
-# endif
-#endif
+ peripheral_request_list(pins, "bfin_mac");
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
/* Initialize the TX DMA channel registers */
- *pDMA2_X_COUNT = 0;
- *pDMA2_X_MODIFY = 4;
- *pDMA2_Y_COUNT = 0;
- *pDMA2_Y_MODIFY = 0;
+ bfin_write_DMA2_X_COUNT(0);
+ bfin_write_DMA2_X_MODIFY(4);
+ bfin_write_DMA2_Y_COUNT(0);
+ bfin_write_DMA2_Y_MODIFY(0);
/* Initialize the RX DMA channel registers */
- *pDMA1_X_COUNT = 0;
- *pDMA1_X_MODIFY = 4;
- *pDMA1_Y_COUNT = 0;
- *pDMA1_Y_MODIFY = 0;
+ bfin_write_DMA1_X_COUNT(0);
+ bfin_write_DMA1_X_MODIFY(4);
+ bfin_write_DMA1_Y_COUNT(0);
+ bfin_write_DMA1_Y_MODIFY(0);
+
+ return 0;
+}
+static int bfin_EMAC_setup_addr(struct eth_device *dev)
+{
+ bfin_write_EMAC_ADDRLO(
+ dev->enetaddr[0] |
+ dev->enetaddr[1] << 8 |
+ dev->enetaddr[2] << 16 |
+ dev->enetaddr[3] << 24
+ );
+ bfin_write_EMAC_ADDRHI(
+ dev->enetaddr[4] |
+ dev->enetaddr[5] << 8
+ );
return 0;
}
return -1;
/* Initialize EMAC address */
- bfin_EMAC_setup_addr(bd);
+ bfin_EMAC_setup_addr(dev);
/* Initialize TX and RX buffer */
for (i = 0; i < PKTBUFSRX; i++) {
rxbuf[i] = SetupRxBuffer(i);
if (i > 0) {
- rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
- &(rxbuf[i]->Dma[0]);
+ rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
if (i == (PKTBUFSRX - 1))
- rxbuf[i]->Dma[1].NEXT_DESC_PTR =
- &(rxbuf[0]->Dma[0]);
+ rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
}
}
for (i = 0; i < TX_BUF_CNT; i++) {
txbuf[i] = SetupTxBuffer(i);
if (i > 0) {
- txbuf[i - 1]->Dma[1].NEXT_DESC_PTR =
- &(txbuf[i]->Dma[0]);
+ txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
if (i == (TX_BUF_CNT - 1))
- txbuf[i]->Dma[1].NEXT_DESC_PTR =
- &(txbuf[0]->Dma[0]);
+ txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
}
}
/* Set RX DMA */
- *pDMA1_NEXT_DESC_PTR = &rxbuf[0]->Dma[0];
- *pDMA1_CONFIG = *((u16 *) (void *)&rxbuf[0]->Dma[0].CONFIG);
+ bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
+ bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
/* Wait MII done */
bfin_miiphy_wait();
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
- *pEMAC_OPMODE = opmode;
+ bfin_write_EMAC_OPMODE(opmode);
return 0;
}
{
debug("Eth_halt: ......\n");
/* Turn off the EMAC */
- *pEMAC_OPMODE = 0x00000000;
+ bfin_write_EMAC_OPMODE(0);
/* Turn off the EMAC RX DMA */
- *pDMA1_CONFIG = 0x0000;
- *pDMA2_CONFIG = 0x0000;
-
-}
-
-void bfin_EMAC_setup_addr(bd_t *bd)
-{
- *pEMAC_ADDRLO =
- bd->bi_enetaddr[0] |
- bd->bi_enetaddr[1] << 8 |
- bd->bi_enetaddr[2] << 16 |
- bd->bi_enetaddr[3] << 24;
- *pEMAC_ADDRHI =
- bd->bi_enetaddr[4] |
- bd->bi_enetaddr[5] << 8;
+ bfin_write_DMA1_CONFIG(0);
+ bfin_write_DMA2_CONFIG(0);
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
- buf = (ADI_ETHER_BUFFER *) (RXBUF_BASE_ADDR + no * total_size);
- frmbuf =
- (ADI_ETHER_FRAME_BUFFER *) (RXBUF_BASE_ADDR + no * total_size +
- nobytes_buffer);
+ buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
+ frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
- buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
+ buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
- buf = (ADI_ETHER_BUFFER *) (TXBUF_BASE_ADDR + no * total_size);
- frmbuf =
- (ADI_ETHER_FRAME_BUFFER *) (TXBUF_BASE_ADDR + no * total_size +
- nobytes_buffer);
+ buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
+ frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
uchar buf[64];
int i, value = 0;
int length;
+ uint addr;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
- buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF);
- buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8);
- buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16);
- buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24);
- buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF);
- buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8);
+ addr = bfin_read_EMAC_ADDRLO();
+ buf[0] = buf[6] = addr;
+ buf[1] = buf[7] = addr >> 8;
+ buf[2] = buf[8] = addr >> 16;
+ buf[3] = buf[9] = addr >> 24;
+ addr = bfin_read_EMAC_ADDRHI();
+ buf[4] = buf[10] = addr;
+ buf[5] = buf[11] = addr >> 8;
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
for (i = 0; i < 42; i++)
buf[i + 22] = i;
printf("--------Send 64 bytes......\n");
- bfin_EMAC_send(NULL, (volatile void *)buf, 64);
+ bfin_EMAC_send(NULL, buf, 64);
for (i = 0; i < 100; i++) {
udelay(10000);
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
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