#include <common.h>
#include <command.h>
+#include <cpsw.h>
#include <net.h>
#include <miiphy.h>
#include <malloc.h>
#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
#define for_active_slave(slave, priv) \
- slave = (priv)->slaves + (priv)->data.active_slave; if (slave)
+ slave = (priv)->slaves + (priv)->data->active_slave; if (slave)
#define for_each_slave(slave, priv) \
for (slave = (priv)->slaves; slave != (priv)->slaves + \
(priv)->data->slaves; slave++)
static void cpsw_slave_update_link(struct cpsw_slave *slave,
struct cpsw_priv *priv, int *link)
{
- struct phy_device *phy;
+ struct phy_device *phy = priv->phydev;
u32 mac_control = 0;
int retries = NUM_TRIES;
struct phy_device *phydev;
u32 supported = PHY_GBIT_FEATURES;
- if (slave->data->phy_id < 0) {
+ if (slave->data->phy_addr < 0) {
u32 phy_addr;
for (phy_addr = 0; phy_addr < 32; phy_addr++) {
}
} else {
phydev = phy_connect(priv->bus,
- slave->data->phy_id,
+ slave->data->phy_addr,
dev,
slave->data->phy_if);
}
struct cpsw_slave *slave;
void *regs = (void *)data->cpsw_base;
struct eth_device *dev;
- int i;
int idx = 0;
debug("%s@%d\n", __func__, __LINE__);
priv->host_port_regs = regs + data->host_port_reg_ofs;
priv->dma_regs = regs + data->cpdma_reg_ofs;
priv->ale_regs = regs + data->ale_reg_ofs;
- priv->descs = (void *)regs + data->bd_ram_ofs;
for_each_slave(slave, priv) {
cpsw_slave_setup(slave, idx, priv);
cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
priv->bus = miiphy_get_dev_by_name(dev->name);
- for_active_slave(slave, priv) {
+ for_active_slave(slave, priv)
ret = cpsw_phy_init(dev, slave);
- if (ret < 0)
- break;
- }
+
return ret;
}