* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
-/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */
-/* Should be fairly simple to make it work with the PL010 as well */
+/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
+#include <dm.h>
+#include <errno.h>
#include <watchdog.h>
+#include <asm/io.h>
+#include <serial.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <linux/compiler.h>
+#include "serial_pl01x_internal.h"
-#if defined(CFG_PL010_SERIAL) || defined(CFG_PL011_SERIAL)
-
-#include "serial_pl01x.h"
+#ifndef CONFIG_DM_SERIAL
-#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned int *)(addr))
-
-/*
- * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
- * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
- * Versatile PB has four UARTs.
- */
-#define CONSOLE_PORT CONFIG_CONS_INDEX
-#define baudRate CONFIG_BAUDRATE
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
+static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
+static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
-static void pl01x_putc (int portnum, char c);
-static int pl01x_getc (int portnum);
-static int pl01x_tstc (int portnum);
+DECLARE_GLOBAL_DATA_PTR;
+#endif
-#ifdef CFG_PL010_SERIAL
+static int pl01x_putc(struct pl01x_regs *regs, char c)
+{
+ /* Wait until there is space in the FIFO */
+ if (readl(®s->fr) & UART_PL01x_FR_TXFF)
+ return -EAGAIN;
+
+ /* Send the character */
+ writel(c, ®s->dr);
-int serial_init (void)
+ return 0;
+}
+
+static int pl01x_getc(struct pl01x_regs *regs)
{
- unsigned int divisor;
+ unsigned int data;
- /*
- ** First, disable everything.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0);
+ /* Wait until there is data in the FIFO */
+ if (readl(®s->fr) & UART_PL01x_FR_RXFE)
+ return -EAGAIN;
- /*
- ** Set baud rate
- **
- */
- switch (baudRate) {
- case 9600:
- divisor = UART_PL010_BAUD_9600;
- break;
+ data = readl(®s->dr);
- case 19200:
- divisor = UART_PL010_BAUD_9600;
- break;
+ /* Check for an error flag */
+ if (data & 0xFFFFFF00) {
+ /* Clear the error */
+ writel(0xFFFFFFFF, ®s->ecr);
+ return -1;
+ }
- case 38400:
- divisor = UART_PL010_BAUD_38400;
- break;
+ return (int) data;
+}
- case 57600:
- divisor = UART_PL010_BAUD_57600;
- break;
+static int pl01x_tstc(struct pl01x_regs *regs)
+{
+ WATCHDOG_RESET();
+ return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
+}
- case 115200:
- divisor = UART_PL010_BAUD_115200;
+static int pl01x_generic_serial_init(struct pl01x_regs *regs,
+ enum pl01x_type type)
+{
+ switch (type) {
+ case TYPE_PL010:
+ /* disable everything */
+ writel(0, ®s->pl010_cr);
+ break;
+ case TYPE_PL011:
+#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+ /* Empty RX fifo if necessary */
+ if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
+ while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
+ readl(®s->dr);
+ }
+#endif
+ /* disable everything */
+ writel(0, ®s->pl011_cr);
break;
-
default:
- divisor = UART_PL010_BAUD_38400;
+ return -EINVAL;
}
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM,
- ((divisor & 0xf00) >> 8));
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff));
-
- /*
- ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH,
- (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN));
+ return 0;
+}
+static int set_line_control(struct pl01x_regs *regs)
+{
+ unsigned int lcr;
/*
- ** Finally, enable the UART
+ * Internal update of baud rate register require line
+ * control register write
*/
- IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN));
-
+ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
+#ifdef CONFIG_PL011_SERIAL_RLCR
+ {
+ int i;
+
+ /*
+ * Program receive line control register after waiting
+ * 10 bus cycles. Delay be writing to readonly register
+ * 10 times
+ */
+ for (i = 0; i < 10; i++)
+ writel(lcr, ®s->fr);
+
+ writel(lcr, ®s->pl011_rlcr);
+ }
+#endif
+ writel(lcr, ®s->pl011_lcrh);
return 0;
}
-#endif /* CFG_PL010_SERIAL */
-
-#ifdef CFG_PL011_SERIAL
-
-int serial_init (void)
+static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
+ int clock, int baudrate)
{
- unsigned int temp;
- unsigned int divider;
- unsigned int remainder;
- unsigned int fraction;
+ switch (type) {
+ case TYPE_PL010: {
+ unsigned int divisor;
+
+ switch (baudrate) {
+ case 9600:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 19200:
+ divisor = UART_PL010_BAUD_9600;
+ break;
+ case 38400:
+ divisor = UART_PL010_BAUD_38400;
+ break;
+ case 57600:
+ divisor = UART_PL010_BAUD_57600;
+ break;
+ case 115200:
+ divisor = UART_PL010_BAUD_115200;
+ break;
+ default:
+ divisor = UART_PL010_BAUD_38400;
+ }
+
+ writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
+ writel(divisor & 0xff, ®s->pl010_lcrl);
+
+ /* Finally, enable the UART */
+ writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
+ break;
+ }
+ case TYPE_PL011: {
+ unsigned int temp;
+ unsigned int divider;
+ unsigned int remainder;
+ unsigned int fraction;
+
+ /*
+ * Set baud rate
+ *
+ * IBRD = UART_CLK / (16 * BAUD_RATE)
+ * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
+ * / (16 * BAUD_RATE))
+ */
+ temp = 16 * baudrate;
+ divider = clock / temp;
+ remainder = clock % temp;
+ temp = (8 * remainder) / baudrate;
+ fraction = (temp >> 1) + (temp & 1);
+
+ writel(divider, ®s->pl011_ibrd);
+ writel(fraction, ®s->pl011_fbrd);
+
+ set_line_control(regs);
+ /* Finally, enable the UART */
+ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
+ UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
- /*
- ** First, disable everything.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0);
+ return 0;
+}
- /*
- ** Set baud rate
- **
- ** IBRD = UART_CLK / (16 * BAUD_RATE)
- ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
- */
- temp = 16 * baudRate;
- divider = CONFIG_PL011_CLOCK / temp;
- remainder = CONFIG_PL011_CLOCK % temp;
- temp = (8 * remainder) / baudRate;
- fraction = (temp >> 1) + (temp & 1);
+#ifndef CONFIG_DM_SERIAL
+static void pl01x_serial_init_baud(int baudrate)
+{
+ int clock = 0;
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider);
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction);
+#if defined(CONFIG_PL010_SERIAL)
+ pl01x_type = TYPE_PL010;
+#elif defined(CONFIG_PL011_SERIAL)
+ pl01x_type = TYPE_PL011;
+ clock = CONFIG_PL011_CLOCK;
+#endif
+ base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
- /*
- ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH,
- (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN));
+ pl01x_generic_serial_init(base_regs, pl01x_type);
+ pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
+}
- /*
- ** Finally, enable the UART
- */
- IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR,
- (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
- UART_PL011_CR_RXE));
+/*
+ * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
+ * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
+ * Versatile PB has four UARTs.
+ */
+int pl01x_serial_init(void)
+{
+ pl01x_serial_init_baud(CONFIG_BAUDRATE);
return 0;
}
-#endif /* CFG_PL011_SERIAL */
-
-void serial_putc (const char c)
+static void pl01x_serial_putc(const char c)
{
if (c == '\n')
- pl01x_putc (CONSOLE_PORT, '\r');
+ while (pl01x_putc(base_regs, '\r') == -EAGAIN);
- pl01x_putc (CONSOLE_PORT, c);
+ while (pl01x_putc(base_regs, c) == -EAGAIN);
}
-void serial_puts (const char *s)
+static int pl01x_serial_getc(void)
{
- while (*s) {
- serial_putc (*s++);
+ while (1) {
+ int ch = pl01x_getc(base_regs);
+
+ if (ch == -EAGAIN) {
+ WATCHDOG_RESET();
+ continue;
+ }
+
+ return ch;
}
}
-int serial_getc (void)
+static int pl01x_serial_tstc(void)
{
- return pl01x_getc (CONSOLE_PORT);
+ return pl01x_tstc(base_regs);
+}
+
+static void pl01x_serial_setbrg(void)
+{
+ /*
+ * Flush FIFO and wait for non-busy before changing baudrate to avoid
+ * crap in console
+ */
+ while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
+ WATCHDOG_RESET();
+ while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
+ WATCHDOG_RESET();
+ pl01x_serial_init_baud(gd->baudrate);
}
-int serial_tstc (void)
+static struct serial_device pl01x_serial_drv = {
+ .name = "pl01x_serial",
+ .start = pl01x_serial_init,
+ .stop = NULL,
+ .setbrg = pl01x_serial_setbrg,
+ .putc = pl01x_serial_putc,
+ .puts = default_serial_puts,
+ .getc = pl01x_serial_getc,
+ .tstc = pl01x_serial_tstc,
+};
+
+void pl01x_serial_initialize(void)
{
- return pl01x_tstc (CONSOLE_PORT);
+ serial_register(&pl01x_serial_drv);
}
-void serial_setbrg (void)
+__weak struct serial_device *default_serial_console(void)
{
+ return &pl01x_serial_drv;
}
-static void pl01x_putc (int portnum, char c)
+#endif /* nCONFIG_DM_SERIAL */
+
+#ifdef CONFIG_DM_SERIAL
+
+struct pl01x_priv {
+ struct pl01x_regs *regs;
+ enum pl01x_type type;
+};
+
+static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
{
- /* Wait until there is space in the FIFO */
- while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF)
- WATCHDOG_RESET();
+ struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_priv *priv = dev_get_priv(dev);
- /* Send the character */
- IO_WRITE (port[portnum] + UART_PL01x_DR, c);
+ pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
+
+ return 0;
}
-static int pl01x_getc (int portnum)
+static int pl01x_serial_probe(struct udevice *dev)
{
- unsigned int data;
+ struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
+ struct pl01x_priv *priv = dev_get_priv(dev);
- /* Wait until there is data in the FIFO */
- while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE)
- WATCHDOG_RESET();
+ priv->regs = (struct pl01x_regs *)plat->base;
+ priv->type = plat->type;
+ return pl01x_generic_serial_init(priv->regs, priv->type);
+}
- data = IO_READ (port[portnum] + UART_PL01x_DR);
+static int pl01x_serial_getc(struct udevice *dev)
+{
+ struct pl01x_priv *priv = dev_get_priv(dev);
- /* Check for an error flag */
- if (data & 0xFFFFFF00) {
- /* Clear the error */
- IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF);
- return -1;
- }
+ return pl01x_getc(priv->regs);
+}
- return (int) data;
+static int pl01x_serial_putc(struct udevice *dev, const char ch)
+{
+ struct pl01x_priv *priv = dev_get_priv(dev);
+
+ return pl01x_putc(priv->regs, ch);
}
-static int pl01x_tstc (int portnum)
+static int pl01x_serial_pending(struct udevice *dev, bool input)
{
- WATCHDOG_RESET();
- return !(IO_READ (port[portnum] + UART_PL01x_FR) &
- UART_PL01x_FR_RXFE);
+ struct pl01x_priv *priv = dev_get_priv(dev);
+ unsigned int fr = readl(&priv->regs->fr);
+
+ if (input)
+ return pl01x_tstc(priv->regs);
+ else
+ return fr & UART_PL01x_FR_TXFF ? 0 : 1;
}
+static const struct dm_serial_ops pl01x_serial_ops = {
+ .putc = pl01x_serial_putc,
+ .pending = pl01x_serial_pending,
+ .getc = pl01x_serial_getc,
+ .setbrg = pl01x_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_pl01x) = {
+ .name = "serial_pl01x",
+ .id = UCLASS_SERIAL,
+ .probe = pl01x_serial_probe,
+ .ops = &pl01x_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
#endif
projects / karo-tx-uboot.git / blobdiff