karo: fdt: fix panel-dpi support

[karo-tx-uboot.git] / drivers / spi / cadence_qspi_apb.c

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 00a115f3fba74e8f1937b2936886d4417cb5fd63..d05340716ec29cfbf91dea9a74f201d46c3c11b7 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -36,12 +36,6 @@
 
 #define CQSPI_FIFO_WIDTH                       (4)
 
-/* Controller sram size in word */
-#define CQSPI_REG_SRAM_SIZE_WORD               (128)
-#define CQSPI_REG_SRAM_RESV_WORDS              (2)
-#define CQSPI_REG_SRAM_PARTITION_WR            (1)
-#define CQSPI_REG_SRAM_PARTITION_RD            \
-       (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
 #define CQSPI_REG_SRAM_THRESHOLD_WORDS         (50)
 
 /* Transfer mode */
@@ -206,18 +200,16 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
        unsigned int *dest_ptr = (unsigned int *)dest;
        unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
 
-       while (remaining > 0) {
-               if (remaining >= CQSPI_FIFO_WIDTH) {
-                       *dest_ptr = readl(src_ptr);
-                       remaining -= CQSPI_FIFO_WIDTH;
-               } else {
-                       /* dangling bytes */
-                       temp = readl(src_ptr);
-                       memcpy(dest_ptr, &temp, remaining);
-                       break;
-               }
+       while (remaining >= sizeof(dest_ptr)) {
+               *dest_ptr = readl(src_ptr);
+               remaining -= sizeof(src_ptr);
                dest_ptr++;
        }
+       if (remaining) {
+               /* dangling bytes */
+               temp = readl(src_ptr);
+               memcpy(dest_ptr, &temp, remaining);
+       }
 
        return;
 }
@@ -225,24 +217,26 @@ static void cadence_qspi_apb_read_fifo_data(void *dest,
 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
        const void *src, unsigned int bytes)
 {
-       unsigned int temp;
+       unsigned int temp = 0;
+       int i;
        int remaining = bytes;
        unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
        unsigned int *src_ptr = (unsigned int *)src;
 
-       while (remaining > 0) {
-               if (remaining >= CQSPI_FIFO_WIDTH) {
-                       writel(*src_ptr, dest_ptr);
-                       remaining -= sizeof(unsigned int);
-               } else {
-                       /* dangling bytes */
-                       memcpy(&temp, src_ptr, remaining);
-                       writel(temp, dest_ptr);
-                       break;
-               }
-               src_ptr++;
+       while (remaining >= CQSPI_FIFO_WIDTH) {
+               for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
+                       writel(*(src_ptr+i), dest_ptr+i);
+               src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
+               remaining -= CQSPI_FIFO_WIDTH;
+       }
+       if (remaining) {
+               /* dangling bytes */
+               i = remaining/sizeof(dest_ptr);
+               memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
+               writel(temp, dest_ptr+i);
+               for (--i; i >= 0; i--)
+                       writel(*(src_ptr+i), dest_ptr+i);
        }
-
        return;
 }
 
@@ -538,6 +532,9 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
        /* Configure the remap address register, no remap */
        writel(0, plat->regbase + CQSPI_REG_REMAP);
 
+       /* Indirect mode configurations */
+       writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
+
        /* Disable all interrupts */
        writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 
@@ -700,10 +697,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
        writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
               plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-       /* Configure SRAM partition for read. */
-       writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
-              CQSPI_REG_SRAMPARTITION);
-
        /* Configure the opcode */
        rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 
@@ -801,9 +794,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
        writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
               plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 
-       writel(CQSPI_REG_SRAM_PARTITION_WR,
-              plat->regbase + CQSPI_REG_SRAMPARTITION);
-
        /* Configure the opcode */
        reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
        writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);