Update from 2013.01 to 2013.07

[karo-tx-uboot.git] / drivers / spi / ich.h

diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
new file mode 100644 (file)
index 0000000..d2e4b85
--- /dev/null
+++ b/drivers/spi/ich.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * This file is derived from the flashrom project.
+ */
+
+struct ich7_spi_regs {
+       uint16_t spis;
+       uint16_t spic;
+       uint32_t spia;
+       uint64_t spid[8];
+       uint64_t _pad;
+       uint32_t bbar;
+       uint16_t preop;
+       uint16_t optype;
+       uint8_t opmenu[8];
+} __packed;
+
+struct ich9_spi_regs {
+       uint32_t bfpr;                  /* 0x00 */
+       uint16_t hsfs;
+       uint16_t hsfc;
+       uint32_t faddr;
+       uint32_t _reserved0;
+       uint32_t fdata[16];             /* 0x10 */
+       uint32_t frap;                  /* 0x50 */
+       uint32_t freg[5];
+       uint32_t _reserved1[3];
+       uint32_t pr[5];                 /* 0x74 */
+       uint32_t _reserved2[2];
+       uint8_t ssfs;                   /* 0x90 */
+       uint8_t ssfc[3];
+       uint16_t preop;                 /* 0x94 */
+       uint16_t optype;
+       uint8_t opmenu[8];              /* 0x98 */
+       uint32_t bbar;
+       uint8_t _reserved3[12];
+       uint32_t fdoc;
+       uint32_t fdod;
+       uint8_t _reserved4[8];
+       uint32_t afc;
+       uint32_t lvscc;
+       uint32_t uvscc;
+       uint8_t _reserved5[4];
+       uint32_t fpb;
+       uint8_t _reserved6[28];
+       uint32_t srdl;
+       uint32_t srdc;
+       uint32_t srd;
+} __packed;
+
+enum {
+       SPIS_SCIP =             0x0001,
+       SPIS_GRANT =            0x0002,
+       SPIS_CDS =              0x0004,
+       SPIS_FCERR =            0x0008,
+       SSFS_AEL =              0x0010,
+       SPIS_LOCK =             0x8000,
+       SPIS_RESERVED_MASK =    0x7ff0,
+       SSFS_RESERVED_MASK =    0x7fe2
+};
+
+enum {
+       SPIC_SCGO =             0x000002,
+       SPIC_ACS =              0x000004,
+       SPIC_SPOP =             0x000008,
+       SPIC_DBC =              0x003f00,
+       SPIC_DS =               0x004000,
+       SPIC_SME =              0x008000,
+       SSFC_SCF_MASK =         0x070000,
+       SSFC_RESERVED =         0xf80000,
+
+       /* Mask for speed byte, biuts 23:16 of SSFC */
+       SSFC_SCF_33MHZ  =       0x01,
+};
+
+enum {
+       HSFS_FDONE =            0x0001,
+       HSFS_FCERR =            0x0002,
+       HSFS_AEL =              0x0004,
+       HSFS_BERASE_MASK =      0x0018,
+       HSFS_BERASE_SHIFT =     3,
+       HSFS_SCIP =             0x0020,
+       HSFS_FDOPSS =           0x2000,
+       HSFS_FDV =              0x4000,
+       HSFS_FLOCKDN =          0x8000
+};
+
+enum {
+       HSFC_FGO =              0x0001,
+       HSFC_FCYCLE_MASK =      0x0006,
+       HSFC_FCYCLE_SHIFT =     1,
+       HSFC_FDBC_MASK =        0x3f00,
+       HSFC_FDBC_SHIFT =       8,
+       HSFC_FSMIE =            0x8000
+};
+
+enum {
+       SPI_OPCODE_TYPE_READ_NO_ADDRESS =       0,
+       SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =      1,
+       SPI_OPCODE_TYPE_READ_WITH_ADDRESS =     2,
+       SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =    3
+};
+
+enum {
+       ICH_MAX_CMD_LEN         = 5,
+};
+
+struct spi_trans {
+       uint8_t cmd[ICH_MAX_CMD_LEN];
+       int cmd_len;
+       const uint8_t *out;
+       uint32_t bytesout;
+       uint8_t *in;
+       uint32_t bytesin;
+       uint8_t type;
+       uint8_t opcode;
+       uint32_t offset;
+};
+
+struct ich_spi_slave {
+       struct spi_slave slave;
+       struct spi_trans trans; /* current transaction in progress */
+       int speed;              /* SPI speed in Hz */
+};