Merge 'u-boot-atmel/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / drivers / usb / musb / musb_core.h

diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index f0f0301bd1f70ec986a87bce6c0207532810a132..ec8a038c74c10e08383b6854729ad72231049eaa 100644 (file)
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -34,7 +34,6 @@
 #ifndef __MUSB_HDRC_DEFS_H__
 #define __MUSB_HDRC_DEFS_H__
 
-#include <usb.h>
 #include <usb_defs.h>
 #include <asm/io.h>
 
@@ -112,7 +111,10 @@ struct musb_regs {
        u16     rxfifoadd;
        u32     vcontrol;
        u16     hwvers;
-       u16     reserved2[5];
+       u16     reserved2a[1];
+       u8      ulpi_busctl;
+       u8      reserved2b[1];
+       u16     reserved2[3];
        u8      epinfo;
        u8      raminfo;
        u8      linkinfo;
@@ -133,7 +135,7 @@ struct musb_regs {
                u8      rxhubport;
        } tar[16];
        /*
-        * end point registers
+        * endpoint registers
         * ep0 elements are valid when array index is 0
         * otherwise epN is valid
         */
@@ -142,7 +144,7 @@ struct musb_regs {
                struct musb_epN_regs epN;
        } ep[16];
 
-} __attribute__((packed, aligned(32)));
+} __attribute__((packed));
 #endif
 
 /*
@@ -181,6 +183,10 @@ struct musb_regs {
 #define MUSB_DEVCTL_HR         0x02
 #define MUSB_DEVCTL_SESSION    0x01
 
+/* ULPI VBUSCONTROL */
+#define ULPI_USE_EXTVBUS       0x01
+#define ULPI_USE_EXTVBUSIND    0x02
+
 /* TESTMODE */
 #define MUSB_TEST_FORCE_HOST   0x80
 #define MUSB_TEST_FIFO_ACCESS  0x40
@@ -341,6 +347,7 @@ struct musb_config {
        struct  musb_regs       *regs;
        u32                     timeout;
        u8                      musb_speed;
+       u8                      extvbus;
 };
 
 /* externally defined data */
@@ -349,7 +356,7 @@ extern struct musb_regs             *musbr;
 
 /* exported functions */
 extern void musb_start(void);
-extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
+extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 
@@ -361,6 +368,28 @@ extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 # define readb(addr)     (u8)bfin_read16(addr)
 # undef  writeb
 # define writeb(b, addr) bfin_write16(addr, b)
+# undef MUSB_TXCSR_MODE /* not supported */
+# define MUSB_TXCSR_MODE 0
+/*
+ * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
+ * However, it has no ULPI support - so there are no registers at all.
+ * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
+ */
+static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
+{
+       return 0;
+}
+static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
+{}
+#else
+static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
+{
+       return readb(&musbr->ulpi_busctl);
+}
+static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
+{
+       writeb(val, &musbr->ulpi_busctl);
+}
 #endif
 
 #endif /* __MUSB_HDRC_DEFS_H__ */