karo: fdt: fix panel-dpi support

[karo-tx-uboot.git] / drivers / video / atmel_hlcdfb.c

diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index bb4d7d8c1471ad9ca79b203ad4cc7cc03c673c01..30c8ccb3a5bf2a33aa6fd97e6dc7c3589cfca29b 100644 (file)
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -13,6 +13,10 @@
 #include <lcd.h>
 #include <atmel_hlcdc.h>
 
+#if defined(CONFIG_LCD_LOGO)
+#include <bmp_logo.h>
+#endif
+
 /* configurable parameters */
 #define ATMEL_LCDC_CVAL_DEFAULT                0xc8
 #define ATMEL_LCDC_DMA_BURST_LEN       8
@@ -31,10 +35,19 @@
  */
 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
 {
-       lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
-               | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
-               | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
-               panel_info.mmio + ATMEL_LCDC_LUT(regno));
+       lcdc_writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
+               ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk) |
+               ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk) |
+               ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
+}
+
+ushort *configuration_get_cmap(void)
+{
+#if defined(CONFIG_LCD_LOGO)
+       return bmp_logo_palette;
+#else
+       return NULL;
+#endif
 }
 
 void lcd_ctrl_init(void *lcdbase)
@@ -42,11 +55,13 @@ void lcd_ctrl_init(void *lcdbase)
        unsigned long value;
        struct lcd_dma_desc *desc;
        struct atmel_hlcd_regs *regs;
+       u32 clk_pol;
 
        if (!has_lcdc())
                return;     /* No lcdc */
 
-       regs = (struct atmel_hlcd_regs *)panel_info.mmio;
+       regs = panel_info.mmio;
+       clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0;
 
        /* Disable DISP signal */
        lcdc_writel(&regs->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
@@ -78,8 +93,8 @@ void lcd_ctrl_init(void *lcdbase)
                                        | LCDC_LCDCFG0_CGDISHEO
                                        | LCDC_LCDCFG0_CGDISOVR1
                                        | LCDC_LCDCFG0_CGDISBASE
-                                       | panel_info.vl_clk_pol
-                                       | LCDC_LCDCFG0_CLKSEL);
+                                       | LCDC_LCDCFG0_CLKSEL
+                                       | clk_pol);
 
        } else {
                lcdc_writel(&regs->lcdc_lcdcfg0,
@@ -88,7 +103,7 @@ void lcd_ctrl_init(void *lcdbase)
                                | LCDC_LCDCFG0_CGDISHEO
                                | LCDC_LCDCFG0_CGDISOVR1
                                | LCDC_LCDCFG0_CGDISBASE
-                               | panel_info.vl_clk_pol);
+                               | clk_pol);
        }
 
        /* Initialize control register 5 */
@@ -171,6 +186,9 @@ void lcd_ctrl_init(void *lcdbase)
                        | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
        desc->next = (u32)desc;
 
+       /* Flush the DMA descriptor if we enabled dcache */
+       flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+
        lcdc_writel(&regs->lcdc_baseaddr, desc->address);
        lcdc_writel(&regs->lcdc_basectrl, desc->control);
        lcdc_writel(&regs->lcdc_basenext, desc->next);
@@ -194,4 +212,7 @@ void lcd_ctrl_init(void *lcdbase)
        lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
        while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
                udelay(1);
+
+       /* Enable flushing if we enabled dcache */
+       lcd_set_flush_dcache(1);
 }