#define WCR_WDBG 0x02
#define WCR_WDE 0x04 /* WDOG enable */
#define WCR_WDT 0x08
+#define WCR_SRS 0x10
#define WCR_WDW 0x80
#define SET_WCR_WT(x) (x << 8)
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
#endif
timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
- writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
+ writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
hw_watchdog_reset();
}
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
- writew(WCR_WDE, &wdog->wcr);
- writew(0x5555, &wdog->wsr);
- writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
while (1) {
- /*
- * spin for .5 seconds before reset
- */
+ writew(0, &wdog->wcr); /* clear SRS initiating SOFT reset */
}
}