Big white-space cleanup.

[karo-tx-uboot.git] / include / asm-arm / arch-omap24xx / clocks.h

diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h
index 2a95af1810b72a9c66de8c58d5e0192ccd505fba..2e92569a9c29b3640d0824f68daa48247b73e30f 100644 (file)
--- a/include/asm-arm/arch-omap24xx/clocks.h
+++ b/include/asm-arm/arch-omap24xx/clocks.h
@@ -35,9 +35,9 @@
 ; PRCM Scheme II
 ;
 ; Enable clocks and DPLL for:
-;  DPLL=300,   DPLLout=600     M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
-;  Core=600    (core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
-;  MPUF=300    (mpu domain)    2          CM_CLKSEL_MPU[4:0]
+;  DPLL=300,   DPLLout=600     M=1,N=50   CM_CLKSEL1_PLL[21:8]  12/2*50
+;  Core=600    (core domain)   DPLLx2     CM_CLKSEL2_PLL[1:0]
+;  MPUF=300    (mpu domain)    2          CM_CLKSEL_MPU[4:0]
 ;  DSPF=200    (dsp domain)    3          CM_CLKSEL_DSP[4:0]
 ;  DSPI=100                    6          CM_CLKSEL_DSP[6:5]
 ;  DSP_S          bypass                      CM_CLKSEL_DSP[7]
@@ -64,9 +64,9 @@
 ; PRCM Scheme III
 ;
 ; Enable clocks and DPLL for:
-;  DPLL=266,   DPLLout=532     M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
-;  Core=532    (core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
-;  MPUF=266    (mpu domain)    /2          CM_CLKSEL_MPU[4:0]
+;  DPLL=266,   DPLLout=532     M=5+1,N=133 CM_CLKSEL1_PLL[21:8]  12/6*133=266
+;  Core=532    (core domain)   DPLLx2      CM_CLKSEL2_PLL[1:0]
+;  MPUF=266    (mpu domain)    /2          CM_CLKSEL_MPU[4:0]
 ;  DSPF=177.3     (dsp domain)  /3          CM_CLKSEL_DSP[4:0]
 ;  DSPI=88.67                   /6          CM_CLKSEL_DSP[6:5]
 ;  DSP_S         ACTIVATED                 CM_CLKSEL_DSP[7]