Merge branch 'fixes' into cleanups

[karo-tx-uboot.git] / include / asm-avr32 / arch-at32ap700x / clk.h

diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 21545a3c1855cdb546db3172007734418407d674..d83e93b74f6eb06642ac89790cbd6b40f33510c3 100644 (file)
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -26,27 +26,28 @@
 #include <asm/arch/portmux.h>
 
 #ifdef CONFIG_PLL
-#define PLL0_RATE      ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
+#define PLL0_RATE      ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV)     \
+                               * CONFIG_SYS_PLL0_MUL)
 #define MAIN_CLK_RATE  PLL0_RATE
 #else
-#define MAIN_CLK_RATE  (CFG_OSC0_HZ)
+#define MAIN_CLK_RATE  (CONFIG_SYS_OSC0_HZ)
 #endif
 
 static inline unsigned long get_cpu_clk_rate(void)
 {
-       return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
+       return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
 }
 static inline unsigned long get_hsb_clk_rate(void)
 {
-       return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
+       return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
 }
 static inline unsigned long get_pba_clk_rate(void)
 {
-       return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
+       return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
 }
 static inline unsigned long get_pbb_clk_rate(void)
 {
-       return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
+       return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
 }
 
 /* Accessors for specific devices. More will be added as needed. */
@@ -86,7 +87,7 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
 extern void clk_init(void);
 
 /* Board code may need the SDRAM base clock as a compile-time constant */
-#define SDRAMC_BUS_HZ  (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+#define SDRAMC_BUS_HZ  (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
 
 /* Generic clock control */
 enum gclk_parent {
@@ -124,11 +125,11 @@ static inline unsigned long gclk_set_rate(unsigned int id,
 
        switch (parent) {
        case GCLK_PARENT_OSC0:
-               parent_rate = CFG_OSC0_HZ;
+               parent_rate = CONFIG_SYS_OSC0_HZ;
                break;
-#ifdef CFG_OSC1_HZ
+#ifdef CONFIG_SYS_OSC1_HZ
        case GCLK_PARENT_OSC1:
-               parent_rate = CFG_OSC1_HZ;
+               parent_rate = CONFIG_SYS_OSC1_HZ;
                break;
 #endif
 #ifdef PLL0_RATE