Big white-space cleanup.

[karo-tx-uboot.git] / include / asm-mips / au1x00.h

diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 5a00368450cede6cff7c061b3602f3ff7f320df2..6a33197f6cf9db1f950d9a0283a949ce0b5d188e 100644 (file)
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -5,7 +5,7 @@
  *
  * Copyright 2000,2001 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
- *             ppopov@mvista.com or source@mvista.com
+ *        ppopov@mvista.com or source@mvista.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
@@ -119,6 +119,11 @@ static __inline__ int au_ffs(int x)
        return __ilog2(x & -x) + 1;
 }
 
+#define gpio_set(Value)      outl(Value, SYS_OUTPUTSET)
+#define gpio_clear(Value)    outl(Value, SYS_OUTPUTCLR)
+#define gpio_read()          inl(SYS_PINSTATERD)
+#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
+
 #endif /* !ASSEMBLY */
 
 #ifdef CONFIG_PM
@@ -128,7 +133,31 @@ static __inline__ int au_ffs(int x)
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
+#define CP0_IWATCHLO           $18,1
+#define CP0_DEBUG              $23
+
 /* SDRAM Controller */
+#ifdef CONFIG_AU1550
+
+#define MEM_SDMODE0                0xB4000800
+#define MEM_SDMODE1                0xB4000808
+#define MEM_SDMODE2                0xB4000810
+
+#define MEM_SDADDR0                0xB4000820
+#define MEM_SDADDR1                0xB4000828
+#define MEM_SDADDR2                0xB4000830
+
+#define MEM_SDCONFIGA              0xB4000840
+#define MEM_SDCONFIGB              0xB4000848
+#define MEM_SDPRECMD               0xB40008c0
+#define MEM_SDAUTOREF              0xB40008c8
+
+#define MEM_SDWRMD0                0xB4000880
+#define MEM_SDWRMD1                0xB4000888
+#define MEM_SDWRMD2                0xB4000890
+
+#else /* CONFIG_AU1550 */
+
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
 #define MEM_SDMODE2                0xB4000008
@@ -145,6 +174,8 @@ static __inline__ int au_ffs(int x)
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
+#endif /* CONFIG_AU1550 */
+
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034
 
@@ -471,6 +502,8 @@ static __inline__ int au_ffs(int x)
 #define AU1500_ETH0_BASE         0xB1500000
 #define AU1500_ETH1_BASE         0xB1510000
 #define AU1100_ETH0_BASE         0xB0500000
+#define AU1550_ETH0_BASE         0xB0500000
+#define AU1550_ETH1_BASE         0xB0510000
 
 /* 4 byte offsets from AU1000_ETH_BASE */
 #define MAC_CONTROL                     0x0
@@ -520,6 +553,8 @@ static __inline__ int au_ffs(int x)
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define AU1100_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC1_ENABLE       0xB0520004
 
 #define MAC_EN_CLOCK_ENABLE         (1<<0)
 #define MAC_EN_RESET0               (1<<1)
@@ -587,8 +622,8 @@ static __inline__ int au_ffs(int x)
 #define RX_MISSED_FRAME            (1<<31)
 
 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
-                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
-                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+                   RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+                   RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
 #define MAC_RX_BUFF0_ADDR                0x4
 #define RX_DMA_ENABLE               (1<<0)
 #define RX_T_DONE                   (1<<1)
@@ -704,7 +739,6 @@ static __inline__ int au_ffs(int x)
 #define UART_MSR_ANY_DELTA 0x0F        /* Any of the delta bits! */
 
 
-
 /* SSIO */
 #define SSI0_STATUS                0xB1600000
 #define SSI_STATUS_BF              (1<<4)
@@ -825,7 +859,7 @@ static __inline__ int au_ffs(int x)
 #define IR_TX_ENABLE            (1<<12)
 #define IR_LOOPBACK             (1<<14)
 #define IR_SIR_MODE              (IR_SIR | IR_DMA_ENABLE | \
-                                  IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+                                  IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
 #define IR_SIR_FLAGS              (IRDA_BASE+0x24)
 #define IR_ENABLE                 (IRDA_BASE+0x28)
 #define IR_RX_STATUS            (1<<9)
@@ -977,6 +1011,15 @@ static __inline__ int au_ffs(int x)
 #define AC97C_RS              (1<<1)
 #define AC97C_CE              (1<<0)
 
+#define DB1000_BCSR_ADDR 0xAE000000
+#define DB1550_BCSR_ADDR 0xAF000000
+
+#ifdef CONFIG_DBAU1550
+#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
+#else
+#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
+#endif
+
 #ifdef CONFIG_SOC_AU1500
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 /* virtual, kseg0 addr */