/*
* Copyright 2009-2010 eXMeritus, A Boeing Company
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
/* High-level system configuration options */
#define CONFIG_BOOKE /* Power/PowerPC Book-E */
#define CONFIG_E500 /* e500 (Power ISA v2.03 with SPE) */
-#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 family */
#define CONFIG_FSL_ELBC /* FreeScale Enhanced LocalBus Cntlr */
#define CONFIG_FSL_LAW /* FreeScale Local Access Window */
#define CONFIG_P2020 /* FreeScale P2020 */
/* Enable IRQs and watchdog with a 1000Hz system decrementer */
#define CONFIG_CMD_IRQ
-#define CONFIG_SYS_HZ 1000
-
/* -------------------------------------------------------------------- */
#define CONFIG_PCI_PNP /* Scan PCI busses */
#define CONFIG_CMD_PCI /* Enable the "pci" command */
#define CONFIG_FSL_PCI_INIT /* Common FreeScale PCI initialization */
+#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET /* We have PCI-E reset errata */
#define CONFIG_SYS_PCI_64BIT /* PCI resources are 64-bit */
#define CONFIG_PCI_SCAN_SHOW /* Display PCI scan during boot */
/* -------------------------------------------------------------------- */
/* Generic FreeScale hardware I2C support */
-#define CONFIG_HARD_I2C
-#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED 400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
#define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-
-/* I2C bus configuration */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
#define CONFIG_SYS_SPD_BUS_NUM 0
/* Turn off RTC square-wave output to save battery */
#define CONFIG_SYS_RTC_DS1337_NOOSC
-/* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */
+/*
+ * AT24C128N EEPROM at I2C0-0x53.
+ *
+ * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
+ * of 64 bytes per page. The chip uses 2-byte addresses and has a max write
+ * cycle time of 20ms according to the datasheet.
+ *
+ * NOTE: Our environment is stored on regular direct-attached FLASH, this
+ * chip is only used as a write-protected backup for certain key settings
+ * such as the serial# and macaddr values. (EG: "env import")
+ */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
+
+/*
+ * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You
+ * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
+ * will not be able to access the chip.
+ */
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
/* -------------------------------------------------------------------- */
/* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */
+#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */
#define CONFIG_DDR_ECC /* Enable ECC by default */
#define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */
#define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */
#define CONFIG_SYS_CBSIZE 4096 /* Allow up to 4k command lines */
#define CONFIG_SYS_BARGSIZE 4096 /* Allow up to 4k boot args */
#define CONFIG_SYS_HUSH_PARSER /* Enable a fancier shell */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Command-line continuation */
/* A little extra magic here for the prompt */
#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
#define CONFIG_MD5
#define CONFIG_SHA1
#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1
+#define CONFIG_CMD_SHA1SUM
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_SETEXPR
/* Extra environment parameters */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
+ "ethprime=e1000#0\0" \
+ "ethrotate=no\0" \
+ "setbootargs=setenv bootargs " \
+ "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
"perf_mode=performance\0" \
"hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=ulpi\0" \
- "flkernel=0xe8020000\0" \
+ "flkernel=0xe8000000\0" \
"flinitramfs=0xe8800000\0" \
"fldevicetree=0xeff20000\0" \
"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
- "flboot=run preboot; run flbootm\0"
+ "flboot=run preboot; run flbootm\0" \
+ "restore_eeprom=i2c dev 0 && " \
+ "eeprom read $loadaddr 0x0000 0x2000 && " \
+ "env import -c $loadaddr 0x2000\0"
#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blobdiff