Exynos5420: Introduce support for the Peach-Pit board

[karo-tx-uboot.git] / include / configs / M5235EVB.h

diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 5c0dc842aadacfb96cc422e1e70865ba8ebff5a2..0f6e2f72cf01e46f072bbc3d3e73c4b7bd570872 100644 (file)
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -4,23 +4,7 @@
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -40,7 +24,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT        5000    /* timeout in milliseconds, max timeout is 6.71sec */
@@ -75,7 +58,6 @@
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -101,12 +83,11 @@
 #undef CONFIG_MCFPIT
 
 /* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C                /* I2C with hw support */
-#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED           80000
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-#define CONFIG_SYS_I2C_OFFSET          0x00000300
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_i2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       80000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x00000300
 #define CONFIG_SYS_IMMR                CONFIG_SYS_MBAR
 #define CONFIG_SYS_I2C_PINMUX_REG      (gpio->par_qspi)
 #define CONFIG_SYS_I2C_PINMUX_CLR      ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
@@ -152,7 +133,6 @@
 #define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 #define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE+0x20000)
 
-#define CONFIG_SYS_HZ                  1000
 #define CONFIG_SYS_CLK                 75000000
 #define CONFIG_SYS_CPU_CLK             CONFIG_SYS_CLK * 2
 
@@ -167,10 +147,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000 /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x21
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -238,9 +217,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
 #define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_END - 8)
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_END - 4)
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINV)
 #define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
                                         CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \