CONFIGS: peach-pit: Enable display for peach_pit board

[karo-tx-uboot.git] / include / configs / M5253EVBE.h

diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index c2cd62ba702b6d5bdb85526c6e8ae950d6e9b6cc..fabfdb93dbdbfdc6e39a82fd2afb4d35ea57b8f3 100644 (file)
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -2,23 +2,7 @@
  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _M5253EVBE_H
@@ -33,7 +17,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG         /* disable watchdog */
 
@@ -64,6 +47,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
@@ -91,9 +75,7 @@
 #define CONFIG_SYS_ATA_REG_OFFSET      0xA0    /* Offset for normal register accesses */
 #define CONFIG_SYS_ATA_ALT_OFFSET      0xC0    /* Offset for alternate registers */
 #define CONFIG_SYS_ATA_STRIDE          4       /* Interval between registers */
-#define _IO_BASE               0
 
-#define CONFIG_SYS_PROMPT              "=> "
 #define CONFIG_SYS_LONGHELP            /* undef to save memory */
 
 #if defined(CONFIG_CMD_KGDB)
@@ -110,8 +92,6 @@
 #define CONFIG_SYS_MEMTEST_START       0x400
 #define CONFIG_SYS_MEMTEST_END         0x380000
 
-#define CONFIG_SYS_HZ                  1000
-
 #undef CONFIG_SYS_PLL_BYPASS           /* bypass PLL for test purpose */
 #define CONFIG_SYS_FAST_CLK
 #ifdef CONFIG_SYS_FAST_CLK
@@ -135,9 +115,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -164,9 +143,10 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 #define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN           (CONFIG_SYS_SDRAM_SIZE << 20)
 
 /* FLASH organization */
-#define CONFIG_SYS_FLASH_BASE          0xffe00000
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
 #define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      35      /* max number of sectors on one chip */
 #define CONFIG_SYS_FLASH_ERASE_TOUT    1000
@@ -179,24 +159,26 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_FLASH_BASE | \
+                                        CF_ADDRMASK(2) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_CEIB | \
+                                        CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C              0xF0
 
-#define CONFIG_SYS_CSAR0               0xFFE0
-#define CONFIG_SYS_CSMR0               0x001F0021
-#define CONFIG_SYS_CSCR0               0x1D80
-
-#define CONFIG_SYS_CSAR1               0
-#define CONFIG_SYS_CSMR1               0
-#define CONFIG_SYS_CSCR1               0
-
-#define CONFIG_SYS_CSAR2               0
-#define CONFIG_SYS_CSMR2               0
-#define CONFIG_SYS_CSCR2               0
-
-#define CONFIG_SYS_CSAR3               0
-#define CONFIG_SYS_CSMR3               0
-#define CONFIG_SYS_CSCR3               0
+#define CONFIG_SYS_CS0_BASE            0xFFE00000
+#define CONFIG_SYS_CS0_MASK            0x001F0021
+#define CONFIG_SYS_CS0_CTRL            0x00001D80
 
 /*-----------------------------------------------------------------------
  * Port configuration