at91sam9260ek: move board id setup to config header

[karo-tx-uboot.git] / include / configs / M5282EVB.h

diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index a8a265564d5e3ec0a9264e617d2425f302949f4d..706e3d651343e4897db3be847c1f403f5622a42c 100644 (file)
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -41,7 +41,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_MONITOR_IS_IN_RAM        /* define if monitor is started from a pre-loader */
 
@@ -64,6 +63,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
@@ -73,7 +73,6 @@
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -153,9 +152,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x10000 /* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000 /* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -165,16 +163,16 @@
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 #define        CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE          0xffe00000
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
 #define        CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE    0x21
 
 /* If M5282 port is fully implemented the monitor base will be behind
  * the vector table. */
-#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
 #define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH_BASE + 0x400)
 #else
-#define CONFIG_SYS_MONITOR_BASE        (TEXT_BASE + 0x418)     /* 24 Byte for CFM-Config */
+#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_TEXT_BASE + 0x418)  /* 24 Byte for CFM-Config */
 #endif
 
 #define CONFIG_SYS_MONITOR_LEN         0x20000
@@ -209,21 +207,25 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_DISD | \
+                                        CF_CACR_CEIB | CF_CACR_DBWE | \
+                                        CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE            CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE            2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH           16
-#define CONFIG_SYS_CS0_RO              0
-#define CONFIG_SYS_CS0_WS              6
-/*
-#define CONFIG_SYS_CS3_BASE            0xE0000000
-#define CONFIG_SYS_CS3_SIZE            1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH           16
-#define CONFIG_SYS_CS3_RO              0
-#define CONFIG_SYS_CS3_WS              6
-*/
+#define CONFIG_SYS_CS0_BASE            0xFFE00000
+#define CONFIG_SYS_CS0_CTRL            0x00001980
+#define CONFIG_SYS_CS0_MASK            0x001F0001
+
 /*-----------------------------------------------------------------------
  * Port configuration
  */