Merge branch 'master' of git://git.denx.de/u-boot-i2c

[karo-tx-uboot.git] / include / configs / M53017EVB.h

diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 07c85c4f5e72794b37d9d1ac7de3ff92aa6db8f0..0ced196489a3ac463dae0ef441581a5e935389b9 100644 (file)
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -4,23 +4,7 @@
  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+ 
  */
 
 /*
@@ -40,7 +24,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                        115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT                5000
@@ -64,11 +47,12 @@
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
 #      define CONFIG_SYS_RX_ETH_BUFFER 8
+#      define CONFIG_SYS_TX_ETH_BUFFER 8
+#      define CONFIG_SYS_FEC_BUF_USE_SRAM
 #      define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #      define CONFIG_HAS_ETH1
 
@@ -77,6 +61,9 @@
 #      define CONFIG_SYS_FEC1_PINMUX   0
 #      define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
 #      define MCFFEC_TOUT_LOOP         50000
+
+#      define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
+
 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 #      ifndef CONFIG_SYS_DISCOVER_PHY
 #              define FECDUPLEX        FULL
@@ -98,12 +85,11 @@
 #undef CONFIG_MCFPIT
 
 /* I2C */
-#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C                        /* I2C with hw support */
-#undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED           80000
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-#define CONFIG_SYS_I2C_OFFSET          0x58000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       80000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x58000
 #define CONFIG_SYS_IMMR                        CONFIG_SYS_MBAR
 
 #define CONFIG_BOOTDELAY               1       /* autoboot after 5 seconds */
@@ -162,10 +148,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_END                0x20000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL       0x21
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_RAM_SIZE               0x20000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL       0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -177,7 +162,7 @@
 #define CONFIG_SYS_SDRAM_SIZE          64      /* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1          0x43711630
 #define CONFIG_SYS_SDRAM_CFG2          0x56670000
-#define CONFIG_SYS_SDRAM_CTRL          0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL          0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD          0x80010000
 #define CONFIG_SYS_SDRAM_MODE          0x00CD0000
 
@@ -204,7 +189,9 @@
 #define CONFIG_SYS_FLASH_CFI
 #ifdef CONFIG_SYS_FLASH_CFI
 #      define CONFIG_FLASH_CFI_DRIVER          1
-#      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
+#      define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
+#      define CONFIG_FLASH_SPANSION_S29WS_N    1
+#      define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 #      define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 #      define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 #      define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
@@ -226,6 +213,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+                                        CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */