Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / include / configs / M5373EVB.h

diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index a1bc32a6d85526bd50ccf2d8fae69388b5eb30b3..d0044b142d297b09affe517d1c4b8929c004597f 100644 (file)
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -68,7 +68,6 @@
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -124,8 +123,8 @@
        "u-boot=u-boot.bin\0"   \
        "load=tftp ${loadaddr) ${u-boot}\0"     \
        "upd=run load; run prog\0"      \
-       "prog=prot off 0 2ffff;"        \
-       "era 0 2ffff;"  \
+       "prog=prot off 0 3ffff;"        \
+       "era 0 3ffff;"  \
        "cp.b ${loadaddr} 0 ${filesize};"       \
        "save\0"        \
        ""
@@ -162,10 +161,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_END        0x8000  /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x8000  /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x221
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -196,6 +194,7 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 #define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN           (CONFIG_SYS_SDRAM_SIZE << 20)
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -215,7 +214,6 @@
 #      define CONFIG_SYS_NAND_BASE             CONFIG_SYS_CS2_BASE
 #      define CONFIG_SYS_NAND_SIZE             1
 #      define CONFIG_SYS_NAND_BASE_LIST        { CONFIG_SYS_NAND_BASE }
-#      define NAND_MAX_CHIPS           1
 #      define NAND_ALLOW_ERASE_ALL     1
 #      define CONFIG_JFFS2_NAND        1
 #      define CONFIG_JFFS2_DEV         "nand0"
@@ -231,13 +229,23 @@
 #define CONFIG_ENV_OFFSET              0x4000
 #define CONFIG_ENV_SECT_SIZE   0x2000
 #define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_IS_EMBEDDED 1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+                                        CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */