Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / include / configs / M5485EVB.h

diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 971cb67bad1097c7c693f23530af13bea791948d..3487e49a1c36c510590751576ee91f54e183e881 100644 (file)
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -41,7 +41,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT        5000    /* timeout in milliseconds, max timeout is 6.71sec */
@@ -67,7 +66,6 @@
 
 #define CONFIG_FSLDMAFEC
 #ifdef CONFIG_FSLDMAFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_HAS_ETH1
@@ -157,7 +155,7 @@
        "load=tftp ${loadaddr) ${u-boot}\0"     \
        "upd=run load; run prog\0"              \
        "prog=prot off bank 1;"                 \
-       "era ff800000 ff82ffff;"                \
+       "era ff800000 ff83ffff;"                \
        "cp.b ${loadaddr} ff800000 ${filesize};"\
        "save\0"                                \
        ""
@@ -196,13 +194,12 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0xF2000000
-#define CONFIG_SYS_INIT_RAM_END        0x1000  /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR      (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR      (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 #define CONFIG_SYS_INIT_RAM1_END       0x1000  /* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM1_CTRL      0x21
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -230,8 +227,9 @@
 #define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 
 #define CONFIG_SYS_BOOTPARAMS_LEN      64*1024
-#define CONFIG_SYS_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc() */
 
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN          (256 << 10)
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -261,10 +259,11 @@
 #endif
 
 /* Configuration for environment
- * Environment is embedded in u-boot in the second sector of the flash
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
  */
-#define CONFIG_ENV_OFFSET              0x2000
-#define CONFIG_ENV_SECT_SIZE   0x2000
+#define CONFIG_ENV_OFFSET              0x40000
+#define CONFIG_ENV_SECT_SIZE   0x10000
 #define CONFIG_ENV_IS_IN_FLASH 1
 
 /*-----------------------------------------------------------------------
@@ -272,6 +271,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA + \
+                                        CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_BCINVA | \
+                                        CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
+                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
+                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */