mpc83xx: accommodate larger kernel sizes by default

[karo-tx-uboot.git] / include / configs / MPC8315ERDB.h

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index add65f03d059166fd5ae77cd18d8e7b0645dca78..84cc9fa41ea02ce15e736df16c9b1c7e7b2423ff 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
@@ -29,8 +29,8 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300            1 /* E300 family */
-#define CONFIG_MPC83XX         1 /* MPC83xx family */
-#define CONFIG_MPC831X         1 /* MPC831x CPU family */
+#define CONFIG_MPC83xx         1 /* MPC83xx family */
+#define CONFIG_MPC831x         1 /* MPC831x CPU family */
 #define CONFIG_MPC8315         1 /* MPC8315 CPU specific */
 #define CONFIG_MPC8315ERDB     1 /* MPC8315ERDB board specific */
 
@@ -72,6 +72,7 @@
 #define CONFIG_SYS_SICRL               0x00000000 /* 3.3V, no delay */
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_HWCONFIG
 
 /*
  * IMMR new address
@@ -166,7 +167,7 @@
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 
 /*
@@ -223,15 +224,17 @@
  */
 #define CONFIG_SYS_NAND_BASE           0xE0600000      /* 0xE0600000 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_NAND_FSL_ELBC           1
+#define CONFIG_SYS_64BIT_VSPRINTF      /* needed for nand_util.c */
 
-#define CONFIG_SYS_BR1_PRELIM          ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_BR1_PRELIM  ( CONFIG_SYS_NAND_BASE \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V )                /* valid */
-#define CONFIG_SYS_OR1_PRELIM          ( 0xFFFF8000            /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM  ( 0xFFFF8000            /* length 32K */ \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -308,8 +311,28 @@
 #define CONFIG_SYS_PCI_SLV_MEM_BUS     0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE    0x80000000
 
+#define CONFIG_SYS_PCIE1_BASE          0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE      0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE      0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE      0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE          0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE      0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE      0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE      0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000
+
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI        1 /* Use generic PCI setup */
+#define CONFIG_PCIE
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
@@ -323,6 +346,14 @@
 #endif
 
 #define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM                3
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_PHY_TYPE    "utmi"
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
 /*
  * TSEC
@@ -412,7 +443,7 @@
 #define CONFIG_CMD_PCI
 
 #if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -535,7 +566,7 @@
 
 #define CONFIG_BAUDRATE 115200
 
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY 6     /* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS         /* the boot command will set bootargs */
@@ -545,8 +576,9 @@
    "consoledev=ttyS0\0"                                                        \
    "ramdiskaddr=1000000\0"                                             \
    "ramdiskfile=ramfs.83xx\0"                                          \
-   "fdtaddr=400000\0"                                                  \
+   "fdtaddr=780000\0"                                                  \
    "fdtfile=mpc8315erdb.dtb\0"                                         \
+   "usb_phy_type=utmi\0"                                               \
    ""
 
 #define CONFIG_NFSBOOTCOMMAND                                          \