/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_NETTA 1 /* ...on a NetTA board */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
-#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
#define FEC_ENET 1 /* eth.c needs it that way... */
#undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */
#define CONFIG_MII 1
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_PING
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_HUSH_PARSER 1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND 0
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
/***********************************************************************************************************
+------+----------------+------------------------------------------------------------
| # | Name | Comment
+------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
+ | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
| IRQ3 | IRQ_DSP | DSP interrupt
| IRQ4 | IRQ_DSP1 | Extra DSP interrupt
+------+----------------+------------------------------------------------------------
#define ER_BASE 0xF1020000
#define DUMMY_BASE 0xF1FF0000
-/****************************************************************/
-
-/* NAND */
-#define CONFIG_NAND_LEGACY
-#define CONFIG_SYS_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_UNSAFE
-
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* #define NAND_NO_RB */
-
-#define SECTORSIZE 512
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-#define NAND_ChipID_UNKNOWN 0x00
-#define NAND_MAX_FLOORS 1
-#define NAND_MAX_CHIPS 1
-
-/* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */
-#define NAND_DISABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 5)); \
- } while(0)
-
-#define NAND_ENABLE_CE(nand) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 5)); \
- } while(0)
-
-#define NAND_CTL_CLRALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_SETALE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 3)); \
- } while(0)
-
-#define NAND_CTL_CLRCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) &= ~(1 << (15 - 4)); \
- } while(0)
-
-#define NAND_CTL_SETCLE(nandptr) \
- do { \
- (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) |= (1 << (15 - 4)); \
- } while(0)
-
-#ifndef NAND_NO_RB
-#define NAND_WAIT_READY(nand) \
- do { \
- while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 13))) == 0) { \
- WATCHDOG_RESET(); \
- } \
- } while (0)
-#else
-#define NAND_WAIT_READY(nand) udelay(12)
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND_ADDRESS(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define WRITE_NAND(d, adr) \
- do { \
- *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
- } while(0)
-
-#define READ_NAND(adr) \
- ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
-
-#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
-#define CONFIG_JFFS2_DEV "nand0"
-#define CONFIG_JFFS2_PART_SIZE 0x00100000
-#define CONFIG_JFFS2_PART_OFFSET 0x00200000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_JFFS2_CMDLINE
-#define MTDIDS_DEFAULT "nand0=netta-nand"
-#define MTDPARTS_DEFAULT "mtdparts=netta-nand:1m@2m(jffs2)"
-*/
-
/*****************************************************************************/
#define CONFIG_SYS_DIRECT_FLASH_TFTP
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */
#define CONFIG_CDP_PORT_ID "eth%d"
#define CONFIG_CDP_CAPABILITIES 0x00000010
-#define CONFIG_CDP_VERSION "u-boot 1.0" " " __DATE__ " " __TIME__
+#define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
#define CONFIG_CDP_PLATFORM "Intracom NetTA"
#define CONFIG_CDP_TRIGGER 0x20020001
#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
projects / karo-tx-uboot.git / blobdiff