Merge branch 'master' of git://git.denx.de/u-boot-microblaze

[karo-tx-uboot.git] / include / configs / PIP405.h

diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index e301599b8a993e806dffe0b424aa49460b1cfdd2..07415f4b5743fc8420f2646af9ce48dc5970654a 100644 (file)
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -35,6 +35,9 @@
 #define CONFIG_405GP           1       /* This is a PPC405 CPU         */
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_PIP405          1       /* ...on a PIP405 board         */
+
+#define        CONFIG_SYS_TEXT_BASE    0xFFF80000
+
 /***********************************************************
  * Clock
  ***********************************************************/
@@ -71,14 +74,10 @@
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_DOC
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_BSP
 
-
-#define CONFIG_NAND_LEGACY
-
 #define         CONFIG_SYS_HUSH_PARSER
 #define         CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 /**************************************************************
@@ -90,6 +89,7 @@
  * The Atmel EEPROM uses 16Bit addressing.
  ***************************************************************/
 #define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
 #define CONFIG_SYS_I2C_SPEED           50000   /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
@@ -170,6 +170,12 @@
 #define CONFIG_SYS_MEMTEST_START       0x0100000       /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 1 ... 12 MB in DRAM  */
 
+#define CONFIG_CONS_INDEX      1       /* Use UART0                    */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD       691200
 
@@ -252,20 +258,10 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF0000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR        /* inside of On Chip SRAM    */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE        /* End of On Chip SRAM         */
-#define CONFIG_SYS_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE        /* Size of On Chip SRAM        */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
-
-
 /***********************************************************************
  * External peripheral base address
  ***********************************************************************/
@@ -281,7 +277,6 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                1       /* PHY address                  */
-#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/