Merge branch 'master' of git://git.denx.de/u-boot-samsung

[karo-tx-uboot.git] / include / configs / PPChameleonEVB.h

diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
index 8e9d92872a88f03ae5f545e275ec6c0807450594..195925ac5cfd127158199520d8fcbbea5af02e72 100644 (file)
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -75,6 +75,9 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_PPCHAMELEONEVB  1       /* ...on a PPChameleonEVB board */
 
+#define        CONFIG_SYS_TEXT_BASE    0xFFFB0000      /* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_LDSCRIPT    "board/dave/PPChameleonEVB/u-boot.lds"
+
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
 #define CONFIG_MISC_INIT_R     1       /* call misc_init_r()           */
 
@@ -191,6 +194,12 @@
 #define CONFIG_SYS_MEMTEST_START       0x0400000       /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 
+#define CONFIG_CONS_INDEX      1       /* Use UART0                    */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK             /* no external serial clock used */
 #define CONFIG_SYS_BASE_BAUD           691200
 
@@ -414,6 +423,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
@@ -522,10 +532,9 @@
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 
-#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -541,24 +550,15 @@
  * GPIO0[30]   - EMAC0 input
  * GPIO0[31]   - EMAC1 reject packet as output
  */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000550
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1L       0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1L         0x15555444
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_OSRL          0x40000550
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H       0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555444
 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 #define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
-
-
 #define CONFIG_NO_SERIAL_EEPROM
 
 /*--------------------------------------------------------------------*/
@@ -576,17 +576,6 @@
 #define                DIMM_READ_ADDR 0xAB
 #define                DIMM_WRITE_ADDR 0xAA
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register              */
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register       */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register          */
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register    */
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register              */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register            */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register              */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register                 */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                                */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register             */
-
 /* Defines for CPC0_PLLMR1 Register fields */
 #define PLL_ACTIVE             0x80000000
 #define CPC0_PLLMR1_SSCS       0x80000000