Exynos5420: Introduce support for the Peach-Pit board

[karo-tx-uboot.git] / include / configs / RBC823.h

diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h
index d4bcc62e45068ef86117c71ed80e00cc4b1eb808..e7e061cb3e3a1508dba088a2a15a1608f5e52897 100644 (file)
--- a/include/configs/RBC823.h
+++ b/include/configs/RBC823.h
@@ -5,23 +5,7 @@
  * Modified by Udi Finkelstein udif@udif.com
  * For the RBC823 board.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -135,7 +119,6 @@
  * Miscellaneous configurable options
  */
 #define        CONFIG_SYS_LONGHELP                     /* undef to save memory         */
-#define        CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 #if defined(CONFIG_CMD_KGDB)
 #define        CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 #else
@@ -150,8 +133,6 @@
 
 #define        CONFIG_SYS_LOAD_ADDR            0x0100000       /* default load address */
 
-#define        CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
-
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
@@ -278,8 +259,8 @@
  */
 #define SCCR_MASK      SCCR_EBDF11
 #define CONFIG_SYS_SCCR        (SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
-                        SCCR_PRQEN   | SCCR_EBDF00   | \
-                        SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+                        SCCR_PRQEN   | SCCR_EBDF00   | \
+                        SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
                         SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
                         SCCR_DFALCD00)
 
@@ -360,7 +341,7 @@
 
 #define CONFIG_SYS_OR1_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
 #define CONFIG_SYS_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
-                         BR_PS_8 | BR_V)
+                         BR_PS_8 | BR_V)
 
 /*
  * BR4 and OR4 (SDRAM)