mpc83xx: Add UPMA configuration to SIMPC8313

[karo-tx-uboot.git] / include / configs / SIMPC8313.h

diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index a616236b77083ccdbf079ffca55e7b6ccba251ba..1a17323a517108db5ac098d3ec2849277425e2d1 100644 (file)
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -32,12 +32,11 @@
 #define CONFIG_NAND_U_BOOT
 
 #define CONFIG_E300                    1
-#define CONFIG_MPC83XX                 1
-#define CONFIG_MPC831X                 1
+#define CONFIG_MPC83xx                 1
+#define CONFIG_MPC831x                 1
 #define CONFIG_MPC8313                 1
 
 #define CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI
 
 #define CONFIG_MISC_INIT_R
 
@@ -112,7 +111,9 @@
 /*
  * Local Bus LCRR and LBCR regs
  */
-#define CONFIG_SYS_LCRR                (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC   LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
 #define CONFIG_SYS_LBC_LBCR    (0x00040000 /* TODO */ \
                                | (0xFF << LBCR_BMT_SHIFT) \
                                | 0xF ) /* 0x0004ff0f */
@@ -125,6 +126,7 @@
 #else
 #define CONFIG_SYS_NAND_BASE           0xE2800000
 #endif
+#define CONFIG_SYS_FPGA_BASE           0xFF000000
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define NAND_MAX_CHIPS                 1
@@ -136,6 +138,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST     0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_RELOC   0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
 #define CONFIG_SYS_NAND_BR_PRELIM      ( CONFIG_SYS_NAND_BASE \
                                        | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -182,6 +185,16 @@
 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM        CONFIG_SYS_LBLAWBAR0_PRELIM
 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
 
+#define CONFIG_SYS_BR1_PRELIM          ( CONFIG_SYS_FPGA_BASE \
+                                       | BR_PS_16 \
+                                       | BR_MS_UPMA \
+                                       | BR_V )
+#define CONFIG_SYS_OR1_PRELIM          ( OR_AM_2MB \
+                                       | OR_UPM_BCTLD)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_2MB)
+
 /*
  * JFFS2 configuration
  */
@@ -189,7 +202,8 @@
 #define CONFIG_JFFS2_DEV       "nand0"
 
 /* mtdparts command line support */
-#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE              /* needed for mtdparts commands */
 #define MTDIDS_DEFAULT         "nand0=nand0"
 #define MTDPARTS_DEFAULT       "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 
@@ -205,6 +219,9 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
 
 #define CONFIG_SYS_BAUDRATE_TABLE      \
        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
@@ -220,7 +237,6 @@
 #define CONFIG_HARD_I2C                        /* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_NOPROBES                {{0,0x69}} /* Don't probe these addrs */
@@ -332,12 +348,12 @@
 #define CONFIG_CMD_JFFS2
 
 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
-       #undef CONFIG_CMD_ENV
+       #undef CONFIG_CMD_SAVEENV
        #undef CONFIG_CMD_LOADS
 #endif
 
 #define CONFIG_CMDLINE_EDITING         1
-
+#define CONFIG_AUTO_COMPLETE           /* add autocompletion support   */
 
 /*
  * Miscellaneous configurable options
@@ -406,8 +422,9 @@
                                | SICRL_ETSEC2_A )
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK      \
-                               | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
+                                HID0_ENABLE_INSTRUCTION_CACHE | \
+                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 
 #define CONFIG_SYS_HID2                HID2_HBE
 
@@ -434,7 +451,7 @@
 #define CONFIG_SYS_IBAT5U      (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L      (0xF0000000 | BATL_PP_10)
+#define CONFIG_SYS_IBAT6L      (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 #define CONFIG_SYS_IBAT7L      (0)