Merge remote-tracking branch 'u-boot-imx/master'

[karo-tx-uboot.git] / include / configs / TASREG.h

diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26f35fd64ad1d5e155af470c18dd8051344..5ad93836227b5277f2593fc0e53852f6c296a60d 100644 (file)
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -4,23 +4,7 @@
  * (C) Copyright 2004
  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -48,7 +32,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                19200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef  CONFIG_WATCHDOG
 
@@ -78,7 +61,6 @@
 
 #define CONFIG_BOOTDELAY       3
 
-#define CONFIG_SYS_PROMPT              "=> "
 #define CONFIG_SYS_LONGHELP                            /* undef to save memory         */
 
 #if defined(CONFIG_CMD_KGDB)
@@ -101,8 +83,6 @@
 #define CONFIG_SYS_MEMTEST_START       0x400
 #define CONFIG_SYS_MEMTEST_END         0x380000
 
-#define CONFIG_SYS_HZ                  1000
-
 /*
  * Clock configuration: enable only one of the following options
  */
@@ -137,19 +117,11 @@
 /*-----------------------------------------------------------------------
  * I2C
  */
-#define        CONFIG_SOFT_I2C
-#define CONFIG_SYS_I2C_SPEED           100000  /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
-#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC32             */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
-/* mask of address bits that overflow into the "EEPROM chip address"   */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    0x01
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
-                                       /* 32 byte page write mode using*/
-                                       /* last 5 bits of the address   */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT            /* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED      100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE      0x7F
 
-#if defined (CONFIG_SOFT_I2C)
 #if 0 /* push-pull */
 #define        SDA             0x00800000
 #define        SCL             0x00000008
@@ -183,15 +155,24 @@
 #define        I2C_ACTIVE      {DIR1|=SDA;}
 #define        I2C_TRISTATE    {DIR1&=~SDA;}
 #endif
-#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC32     */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address     */
+/* mask of address bits that overflow into the "EEPROM chip address"   */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    0x01
+/*
+ * The Catalyst CAT24WC32 has 32 byte page write mode using
+ * last 5 bits of the address
+ */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x1000  /* End of used area in internal SRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* Size of used area in internal SRAM   */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_ENV_IS_IN_FLASH 1
@@ -252,6 +233,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_CEIB | \
+                                        CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */