/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_TEXT_BASE 0x40000000
+
#ifdef CONFIG_LCD /* with LCD controller ? */
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */
+#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_SYS_SMC_RXBUFLEN 128
+#define CONFIG_SYS_MAXIDLE 10
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM823L/uImage\0" \
+ "hostname=TQM823L\0" \
+ "bootfile=TQM823L/uImage\0" \
"fdt_addr=40040000\0" \
"kernel_addr=40060000\0" \
"ramdisk_addr=40200000\0" \
+ "u-boot=TQM823L/u-image.bin\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=prot off 40000000 +${filesize};" \
+ "era 40000000 +${filesize};" \
+ "cp.b 200000 40000000 ${filesize};" \
+ "sete filesize;save\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#endif
+#define CONFIG_NETCONSOLE
+
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
-#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
-#endif
+#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-
-#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
/*
* Low Level Configuration Settings
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
-#define CFG_IMMR 0xFFF00000
+#define CONFIG_SYS_IMMR 0xFFF00000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
-#define CFG_INIT_RAM_ADDR CFG_IMMR
-#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0x40000000
-#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_FLASH_BASE 0x40000000
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
/* use CFI flash driver */
-#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_USE_BUFFER_WRITE 1
-#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
-#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
-#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
-#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
+#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
+ "128k(dtb)," \
+ "1664k(kernel)," \
+ "2m(rootfs)," \
+ "4m(data)"
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
-#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
-#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
-#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else /* we must activate GPL5 in the SIUMCR for CAN */
-#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
-#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
-#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
-#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*/
-#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
-#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
*-----------------------------------------------------------------------
*
*/
-#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR (0xEC000000)
-#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET 0x0100
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
-#define CFG_DER 0
+#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
-#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
+#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing:
*/
-#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
-#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
-#define CFG_OR1_REMAP CFG_OR0_REMAP
-#define CFG_OR1_PRELIM CFG_OR0_PRELIM
-#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
/*
* BR2/3 and OR2/3 (SDRAM)
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CFG_OR_TIMING_SDRAM 0x00000A00
+#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
-#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#ifndef CONFIG_CAN_DRIVER
-#define CFG_OR3_PRELIM CFG_OR2_PRELIM
-#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
-#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
-#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
-#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
-#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
+#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
+#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
BR_PS_8 | BR_MS_UPMB | BR_V )
#endif /* CONFIG_CAN_DRIVER */
* 80 Mhz => 80.000.000 / Divider = 156
*/
-#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-#define CFG_MAMR_PTA 98
+#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA 98
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
- * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
- * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
+ * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
-#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
-#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
-#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
-#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
-#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_HWCONFIG 1
#endif /* __CONFIG_H */
projects / karo-tx-uboot.git / blobdiff